Motion video signal processing for recording or reproducing – Local trick play processing – With randomly accessible medium
Reexamination Certificate
1997-07-17
2002-04-16
Chevalier, Robert (Department: 2615)
Motion video signal processing for recording or reproducing
Local trick play processing
With randomly accessible medium
C386S349000
Reexamination Certificate
active
06374033
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal processing apparatus for performing processing such as coding, decoding of the like of various kinds of data, e.g., image data and the like.
2. Related Background Art
Conventionally, various apparatuses that encode various kinds of data in huge data volumes to reduce their data volume and allow transmission at relatively low transmission rates have been developed.
For example, in a digital VTR which records image data on a recording medium such as a magnetic tape or the like, standards for recording input image data of about 124 Mbps on a magnetic tape by compressing it to nearly ⅕ (about 25 Mbps), and reproducing the compressed data have been defined.
In the digital VTR complying with such standards, input data is DCT (Discrete Cosine Transform)-transformed and the transformed data is quantized. Then, the quantized data is variable-length-coded to attain data compression. Furthermore, the quantization step upon quantizing data is varied based on various parameters, and rate control is done to obtain constant data volumes after variable-length coding.
Also, MPEG standards that compress input image data using inter-frame or inter-field motion compensated predictive coding, and further compress the predictive coded data using the above-mentioned DCT, quantization, and variable-length coding have been proposed. Various apparatuses such as CD-ROMs and the like that correspond to such standards have been developed.
In the above-mentioned apparatuses such as the digital VTR, CD-ROM, and the like, various kinds of signal processing must be done in real time. In order to realize such real-time processing, a plurality of memories corresponding to various kinds of signal processing are used, resulting in an increase in cost of the entire device.
SUMMARY OF THE INVENTION
Under the circumstances described above, it is one object of the present invention is to provide a signal processing apparatus and method, that can attain a cost reduction and down-sizing of the entire device by reducing memories.
In order to achieve the above object, according to one preferred embodiment of the present invention, there is provided a signal processing apparatus for performing signal processing of image data in units of blocks each consisting of n (vertical)×m (horizontal) pixels, comprising: a memory for storing the image data; division means for dividing image data in one horizontal period of the image data into burst lengths, each of which equals at least a multiple of m and in which the multiple of m×n is not more than a capacity of the memory; and allocation means for allocating data sequences of the burst length at an identical row address so that all image data in the block are aligned at the identical row address.
According to another preferred embodiment of the present invention, there is provided a signal processing apparatus comprising: memory means for storing data to be processed and other data; signal processing means for performing predetermined signal processing for the data while accessing the memory means; and control means for controlling read/write of the data with respect to the memory means, wherein the control means allocates the data in the memory means in accordance with a processing order and a processing unit by the signal processing means, and stores the other data which is not to be processed in an empty area in the memory means.
According to still another preferred embodiment of the present invention, there is provided a storage method for storing image data in a memory to perform signal processing of the image data in units of blocks each consisting of n (vertical)×m (horizontal) pixels, comprising the steps of: dividing image data in one horizontal period of the image data into blocks each having a burst length, which equals at least a multiple of m and in which the multiple of m×n is not more than a capacity of the memory; and allocating data sequences of the burst length at an identical row address so that all image data in the block are aligned at the identical row address.
According to still another preferred embodiment of the present invention, there is provided a signal processing method comprising the steps of: storing data to be processed and other data in a memory; performing predetermined signal processing for the data while accessing the memory; and controlling read/write of the data with respect to the memory, wherein the control step includes the step of allocating the data in the memory in accordance with a processing order and a processing unit in the signal processing step, and storing the other data which is not to be processed in an empty area in the memory.
Other objects, features and advantages of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5450130 (1995-09-01), Foley
patent: 5675387 (1997-10-01), Hoogenboom et al.
patent: 44412955 (1996-05-01), None
patent: 0710029 (1996-05-01), None
Institute of Electrical and Electronics Engineers; Winzker M. et al; “Architecture and Memory Requirements for Stand-alone and Hierarchical MPEG2 HDTV-Decoders with Synchronous Drams”; International Symposium on Circuits and Systems (ISCAS); vol. 1, pp. 609-612.
Institute of Electrical and Electronics Engineers; Matsumura T. et al.; “A Chip Set Architecture for Programmable Real-Time MPEG2 Video Encoder”, Proceedings of the Custom Integrated Circuits Conference,; NR. Conf. 17, pp. 393-396.
Institute of Electrical and Electronics Engineers; Fujiwara a. et al.; “A 200 MHz 16 Mbit Synchronous DRAM with Block Access Mode” 1994 Symposium on VLSI Circuits. Digest of Technical Paper, Proceedings of 1994 IEEE Symposium on VLSI Circuits, 1994, pp. 79-80.
Kizaki Y. et al.; 4-/16-Mbit Synchronous Dram for High-Speed Image Processing:; Hitachi Review; vol. 43, No. 5, Oct. 1, 1994, pp. 217-220.
Jones F.; “A New Era of Fast Dynamic Rams”; IEEE Spectrum, vol. 29, No. 10, Oct. 1, 1992, pp. 43-45, 48-49.
Schmidt R.L.; “a Memory Control Chip for Formatting Data into Blocks Suitable for Video Coding Applications”; IEEE Transactions on Circuits and Systems; vol. 36, No. 10, Oct. 1, 1989, pp. 1275-1280.
Canon Kabushiki Kaisha
Chevalier Robert
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