Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
2001-02-27
2004-09-14
Moe, Aung (Department: 2612)
Television
Camera, system and detail
Solid-state image sensor
C348S303000
Reexamination Certificate
active
06791613
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal processing apparatus having a clamping capacity.
2. Related Background Art
For the solid-state image pickup apparatus, CCD has been conventionally employed because of its high S/N ratio. On the other hand, there has been developed so-called amplifying-type solid-state image pickup apparatus which is featured by the simplicity of use and the low electric power consumption. The amplifying solid-state image pickup apparatus is to guide a signal charge accumulated in a light receiving pixel to a control electrode of a transistor provided in the pixel portion and to output an amplified signal from a main electrode, and is known in various types such as an SIT image sensor utilizing an SIT (static induction transistor) as the amplifying transistor, a bipolar image sensor utilizing a bipolar transistor, a CMD utilizing a JFET (junction field effect transistor) in which the control electrode (gate) is depleted, and a CMOS sensor utilizing a MOS transistor. Intensive development is being conducted for the CMOS transistor, since it matches well with the CMOS process and allows to form peripheral CMOS circuits on a single chip. In such amplifying solid-state image pickup apparatus however, the output offset of the amplifying transistor in each pixel is different from pixel to pixel, so that a fixed pattern noise (FPN) is superposed with the output signal of the image sensor. There have been proposed various signal output circuits in order to eliminate such FPN. In the following there will be explained a representative example of such CMOS sensor.
FIG. 1
is a circuit diagram of a conventional CMOS image sensor and a readout circuit therefor, showing unit pixels
1
illustrated in a 2×2 matrix arrangement for the purpose of simplicity. In
FIG. 1
there are shown a photodiode
2
for accumulating a signal charge by receiving light, a MOS transistor
3
for amplifying the signal charge, a transfer MOS transistor
4
for transferring the signal charge accumulated in the photodiode
2
to the gate electrode of the MOS transistor
3
, a reset MOS transistor
5
for resetting the gate electrode potential of the MOS transistor
3
, and a power supply potential supply line
6
to which commonly connected are the drain electrode of the reset MOS transistor
5
and the drain electrode of the amplifying MOS transistor
3
. There are also shown a selector switch MOS transistor
7
for selecting an output pixel, and a pixel output line
8
. When the selector switch MOS transistor
7
is turned on, the source electrode of the amplifying MOS transistor and the output line
8
are connected whereby the signal output of a selected pixel is guided to the output line
8
. A constant current supply MOS transistor
9
for feeding a constant current to the pixel output line
8
, which supplies the amplifying MOS transistor
3
with a load current through the selector switch MOS transistor
7
, thereby causing the amplifying MOS transistor
3
to function as a source follower and outputting to the output line
8
a potential corresponding to the gate potential of the MOS transistor
3
with a constant voltage difference. There are also shown a transfer control line
10
for controlling the gate potential of the transfer MOS transistor
4
, a reset control line
11
for controlling the gate potential of the reset MOS transistor
5
, a selection control line
12
for controlling the gate potential of the selecting MOS transistor
7
, a constant potential supply line
13
for supplying the gate of the MOS transistor
9
with a constant potential thereby causing the MOS transistor
9
to operate in a saturation region thereby constituting a constant current supply source, a pulse terminal
14
for supplying the transfer control line
10
with a transfer pulse, a pulse terminal
15
for supplying the reset control line
11
with a reset pulse, a pulse terminal
16
for supplying the selection control line
12
with a selection pulse, a vertical scanning circuit
17
for selecting in succession rows of the pixels in a matrix arrangement, an output line
18
of the vertical scanning circuit
17
, including a first row selecting output line
18
-
1
and a second row selecting output line
18
-
2
, a switching MOS transistor
19
for guiding the pulse from the pulse terminal
14
to the transfer control line
10
, a switching MOS transistor
20
for guiding the pulse from the pulse terminal
15
to the reset control line
11
, and a switching MOS transistor
21
for guiding the pulse from the pulse terminal
16
to the selection control line
12
. The gates of the MOS transistors
19
,
20
,
21
are connected to the row selecting output line
18
, and the row of the pixels to be driven is determined by the state of the row selecting output line
18
. An output readout circuit
22
of a pixel is provided with a capacitance
23
for holding a reset signal output of the pixel, a capacitance
24
for holding a photo signal output of the pixel, a switching MOS transistor
25
for turning on/off the conduction between the pixel output line
8
and the capacitance
23
, a switching MOS transistor
26
for turning on/off the conduction between the pixel output line
8
and the capacitance
24
, a noise output line
27
for guiding the reset output held in the capacitance
23
, a signal output line
28
for guiding the signal output held in the capacitance
24
, a switching MOS transistor
29
for turning on/off the conduction between the capacitance
23
and the noise output line
27
, a switching MOS transistor
30
for turning on/off the conduction between the capacitance
24
and the signal output line
28
, a noise output line resetting MOS transistor
31
for resetting the potential of the noise output line
27
, a signal output line resetting MOS transistor
32
for resetting the potential of the signal output line
28
, a power supply terminal
33
for supplying the source electrodes of the resetting MOS transistors
31
,
32
with a reset potential, and a horizontal scanning circuit
34
for selecting in succession the above-mentioned capacitances
23
,
24
provided in each column of the pixels in a matrix arrangement, including an output line
35
-
1
for selecting a first column and an output line
35
-
2
for selecting a second column. The output line of the horizontal scanning circuit
34
is connected to the gates of the switching MOS transistors
29
,
30
. There are further shown a pulse supply terminal
36
for applying a pulse to the gates of the resetting MOS transistors
31
,
32
, pulse supply terminals
37
,
38
for respectively applying pulses to the gates of the switching MOS transistors
25
,
26
, a differential amplifier
39
for amplifying and outputting the differential voltage between the potential of the noise output line
27
and that of the signal output line
28
, and an output terminal
40
of the differential amplifier
39
.
In the following there will be explained the operation of the sensor shown in
FIG. 1
, with reference to a timing chart shown in FIG.
2
. It is assumed that each of the MOS transistors shown in
FIG. 1
is N type, which is turned on or off respectively when the gate potential is at the high or low level state. In timing pulse &PHgr;
14
to &PHgr;
38
in
FIG. 2
, the suffixes
14
to
38
respectively coincide with the numbers of the pulse input terminals shown in
FIG. 1
, and &PHgr;
14
to &PHgr;
38
indicate the pulses entering the respective input terminals.
At first the vertical scanning circuit
17
shifts the pulse &PHgr;
18-1
supplied to the terminal
18
-
1
to the high level state to enable the operation of the first row of the pixel matrix. When the pulse &PHgr;
16
applied to the terminal
16
is shifted to the high level state, the source of the amplifying MOS transistor
3
of the pixel is connected with the constant current power supply
9
through the output line
8
whereby the output of the source follower of the pixel is outputted to the output l
Noda Tomoyuki
Shinohara Mahito
Fitzpatrick ,Cella, Harper & Scinto
Moe Aung
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