Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
2000-03-24
2003-09-02
Chin, Stephen (Department: 2634)
Pulse or digital communications
Equalizers
Automatic
C375S327000, C375S355000, C375S375000, C375S376000, C329S307000, C329S325000, C329S360000, C327S156000
Reexamination Certificate
active
06614841
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to signal processing apparatuses, and more particularly to a signal processing apparatus in which a received signal or a signal reproduced from a recording medium is subjected to both adaptive equalization and sampling.
2. Description of the Background Art
In hard disk drives and magnetic tape drives where digital data is recorded/reproduced, a PRML (Partial Response Maximum Likelihood) method has been recently applied to detect data. In this method, a reproduced signal is first subjected to partial response equalization and then to maximum likelihood decoding by going through a Viterbi decoder, for example. For data detection under this PRML method, the drive needs to have two functions: a waveform equalization function of accurately subjecting a reproduced signal to partial response equalization; and a function of generating a clock signal which is accurately synchronized with reproduced data for sampling. A description is given next below about a reproduced signal processing part of a conventional hard disk drive applying the PRML method therein.
FIG. 8
is a block diagram showing the structure of a conventional signal processing apparatus used as the reproduced signal processing part of the hard disk drive. In
FIG. 8
, a reproduced signal
1
reproduced from a magnetic recording medium is subjected to partial response equalization in an analog equalizer
2
. The equalized signal is subjected to sampling and digitalization in an AD converter (ADC)
3
with timing of a clock signal
15
, and then is outputted as a sampled signal
4
. The sampled signal
4
is provided to both an adaptive equalizer
5
and a phase error detector
9
. The adaptive equalizer
5
adaptively corrects the sampled signal
4
, depending on a state of the signal, in such a manner as to minimize a deviation from an ideal signal value caused by time-varying change in characteristics of the recording medium or reproduction head, for example, and then outputs an equalized signal
6
. A Viterbi decoder
7
subjects, in consideration of partial response signal correlation, the equalized signal
6
to most likelihood decoding according to Viterbi algorithm, and then detects digital information previously recorded on the recording medium for output as reproduced data
8
.
The phase error detector
9
detects, according to the sampled signal
4
, any deviation of the sample point thereof from an ideal sample point (hereinafter, referred to as phase error). The phase error is resulted from the timing of sampling carried out in the AD converter
3
, and the phase error detector
9
outputs a phase error signal
10
. Note that, an exemplary structure of the phase error detector
9
is found in Roy. D. Cideciyan, et al., “A PRML System for Digital Magnetic Recording”, IEEE Journal on selected areas in Communications, Vol. 10, No. 1, pp. 38-pp. 56 (January. 1992). The phase error signal
10
is converted into an analog signal in a DA converter (DAC)
11
, and the analog signal is subjected to smoothing in a loop filter
12
to be an oscillation frequency control signal
13
. A variable frequency oscillation circuit
14
oscillates in a frequency corresponding to a voltage of the oscillation frequency control signal
13
,.and outputs the clock signal
15
. The clock signal
15
is fed back as a clock for sampling in the AD converter
3
. Since all of the AD converter
3
, the phase error detector
9
, the DA converter
11
, the loop filter
12
, and the variable frequency oscillation circuit
14
structure a PLL (Phase Locked Loop) circuit, the clock signal
15
can be a clock phase-locked to the reproduced data.
With such structure and operation, the conventional signal processing apparatus in
FIG. 8
implements data reproduction under the PRML method.
Reproduced signal processing under such PRML method is found in, for example, J. D. Cocker, et al., “Implementation of PRML in a rigid disk drive”, IEEE Transactions on Magnetics, Vol. 27, No. 6 (November 1991).
As described in the foregoing, the conventional signal processing apparatus in
FIG. 8
so generates the clock signal
15
as to minimize the phase error of the sample point of the sampled signal
4
. From a viewpoint of implementing data reproduction with a lower error rate under the PRML method, it is preferable to so generate the clock signal
15
as to minimize the phase error of a sample point of the equalized signal
6
. In this manner, the clock signal
15
can be more-accurately phase-locked to reproduced data.
Further, in the conventional signal processing apparatus in
FIG. 8
, the analog equalizer
2
is the one which mainly carries out the partial response equalization. However, from viewpoints of improving the degree of accuracy in equalization and simplifying the process of LSI, it is more preferable to carry out the equalization in digital processing.
With such viewpoints, the signal processing apparatus may be structured as shown in FIG.
9
.
FIG. 9
is a block diagram showing the structure of the signal processing apparatus as an exemplary betterment for the conventional one in FIG.
8
. In
FIG. 9
, any constituent found in
FIG. 8
is denoted by the same reference numeral. Differences between these two signal processing apparatuses lie in three respects: the reproduced signal
1
skips the analog equalizer
2
and goes straight to an AD converter
17
; an adaptive equalizer
80
subjects a sampled signal
33
to partial response equalization and also to adaptive equalization in such a manner as to minimize the equalization error; and a signal forwarded to the phase error detector
9
is the equalized signal
6
. Such structure realizes data reproduction under the PRML method at a lower error rate, improvement in equalization accuracy, and a simplified LSI.
In the signal processing apparatus in
FIG. 9
, however, some competitive problem may be caused by two types of feed back control including adaptive equalization and PLL. Such new problem is described next below by referring to
FIGS. 10 and 11
.
FIG. 10
is a block diagram showing the structure of the adaptive equalizer
80
of the signal processing apparatus in FIG.
9
. As shown in
FIG. 10
, the adaptive equalizer
80
is structured by a transversal-type filter with 5 taps and an adaptive controller
28
. The sampled signal
33
is sequentially delayed by going through delay circuits
18
to
21
, which each delays the signal on a data period basis. A coefficient circuit
22
multiplies the sampled signal
33
by a coefficient C(−
2
) and other coefficient circuits
23
to
26
multiply outputs from the delay circuits
18
to
21
, respectively, by coefficients C(−
1
), C(
0
), C(
1
), and C(
2
) for output. An adding circuit
27
adds every output from the coefficient circuits
22
to
26
, and then outputs the sum as the equalized signal
6
. According to the equalized signal
6
, the adaptive controller
28
adaptively controls every coefficient by tap coefficient signals
29
a
to
29
e
in such a manner as to minimize a mean-square error of the signal amplitude of the equalized signal
6
. Such adaptive control is well known as an LMS (Least Means Square) algorithm, and is not described in detail.
The equalized signal
6
generated in the adaptive equalizer
80
is provided both to the Viterbi decoder
7
and the phase error detector
9
. The phase error detector
9
detects any phase error of the sample point of the equalized signal
6
, and then generates the phase error signal
10
. From then onward, the clock signal
15
is generated according to the phase error signal
10
in a similar manner to the signal processing apparatus in
FIG. 8
, and is fed back to the AD converter
17
as a clock for sampling.
By referring to
FIG. 11
, it is described how the phase of the sample point of the equalized signal
6
is shifted by such operation. In
FIG. 11
, a linear line
31
shows the relationship between the phase of the sample point of the equalized signal
6
and the phase error
Chin Stephen
Ha Dac V.
Matsushita Electric - Industrial Co., Ltd.
Wenderoth , Lind & Ponack, L.L.P.
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