Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Reexamination Certificate
1996-05-28
2001-12-04
Harrison, Jessica J. (Department: 3713)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
Least weight routing
C709S241000, C709S241000, C709S241000, C709S241000, C709S241000, C710S244000, C710S264000, C713S500000, C713S502000
Reexamination Certificate
active
06327631
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to processing apparatus for a signal processing network comprising a plurality of interconnected processing units for real time signal processing.
2. Description of the Prior Art
The invention finds particular application for audio signal processing in, for example, an audio mixing console.
Traditionally, audio mixing consoles have been based on discrete technology with audio signal processing modules connected together in a desired relationship and then controlled by manually operable switches on the console. It has been a relatively straightforward task, albeit a skilled and time consuming task, to oversee the physical interconnections necessary during setting up and debugging a desired audio processing structure. However, traditional audio mixing consoles have a number of disadvantages including their physical size, the total number of manually operable controls (fader, potentiometers, switches, etc.), and the relative inflexibility of the overall arrangement.
Accordingly, it has been proposed to provide an audio mixing console comprising a front panel including a plurality of user operable controls for controlling different audio signal processing functions and a digital signal processor for processing audio signals in response to the settings of the user operable controls. It is hoped that such technology can lead to reductions in the overall size of such consoles while at the same time increasing flexibility.
However, in order to be able to process digital audio signals in real time, a highly parallel signal processing structure is required. A problem with the use of a highly parallel processing arrangement for the processing of signals in real time is the scheduling of tasks between the processors and ensuring that the tasks are performed in the correct sequence to avoid, for example, race conditions or signal data, corruption.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention there is provided processing apparatus for a signal processing system comprising means for inputting and outputting audio signals and a network of interconnected processors comprising a plurality of signal processors for digitally processing input signals in real time to generate output signals and one or more control processors for controlling the operation of the signal processors, the processing apparatus comprising means automatically scheduling control tasks in the control processor(s) in a plurality of time slices.
In one embodiment of the invention, a plurality of control processors operate asynchronously, the means for automatically scheduling time slices including time slice coordination means whereby the control processors communicate to coordinate the execution of successive time slices.
In a preferred embodiment of the invention the time slice coordination means comprises a control line connected in common to each control processor and, in each control processor, means for writing a first binary value to the control line during execution of a task for a time slice, means for writing the opposite binary value to the control line on completion of the task for the time slice and means responsive to the opposite binary value being returned on the control line to indicate that all control processors have completed their tasks for that time slice before commencing the next time slice.
In the preferred embodiment of the invention, the control line is connected to each control processor in a wired-OR configuration and the binary value is a binary one value, the opposite binary value being a binary zero value.
A disadvantage of implementing a complex signal processing structure for processing audio samples on a parallel processing network where a lot of interrelated tasks are to be performed is the need to be able to process tasks at the audio sample rate. This puts a constraint on the number of processing slices which can be processed for each audio sample. A resulting difficulty is that some functions, for example a multiplexer function for selecting between different signal sources dependent on a control input for example, can take a number of slices to perform, reducing the number of slices available for implementing other functions.
In accordance with another aspect of the invention, a signal processor comprises a microcode memory for microcode instructions for the signal processor, and a data memory for signal data representative of a plurality of node input variables and at least one node output variable for a signal processing node to be processed in the signal processor, the microcode instructions including at least one address field for identifying the data memory location for a node input variable, and a control processor comprising means for patching at least one address field in at least one microcode instruction in the microcode memory during processing of audio signals by the apparatus for implementing a multiplexer function to select between a plurality of node input variables.
In a preferred embodiment of the invention, the control processor comprises a table of alternative address fields for the microcode instruction address field, means for selecting one of the alternative address fields dependent upon a selection parameter, and means for patching at least the appropriate address field in the microcode instruction in the microcode memory.
Another aspect of the control of the scheduling of tasks is the scheduling of delays, resulting from variable control inputs for example. In accordance with another aspect of the invention, there is provided means for automatically scheduling delays in a control task sequence, the means for automatically scheduling delays comprising a control delay list, means for inserting tasks to be delayed in delay termination order, and means for comparing at least the delayed task at the head of the list to the current time to determine when the task is to be processed.
Preferably, where control processors are not fully occupied, or for a particularly time critical task, a task may be allocated to more than one control processor, each control processor communicating to the other control processors if it completes the task, whereby the other control processors may abandon further processing of the task.
In a preferred embodiment of the invention the apparatus comprises a graphics generator for generating a graphical representation of a configuration of an audio mixing console and of an audio signal processing structure for processing audio signals in accordance with the configuration of the audio mixing console, the graphics converter being arranged to convert the graphical representation of the audio mixing console and the audio signal processing structure into a connectivity map, the automatic scheduling means being responsive to data derived from the connectivity map for scheduling control and audio processing tasks.
A graphical representation of the data processing structure can be readily interpreted by a user and facilitates the setting up and debugging of the data processing structure. In use, the user can set up the interrelationships necessary and identify locations at which signal values should be input or output. It enables a user to design a data processing structure without actually needing to make the physical connections and enables a design to be fully tested. Also, in use it enables an existing design to be modified or tailored- to particular requirements at will. It will be appreciated that this provides significant technical advantages over a conventional approach. The graphical representation, which can for example be generated using a conventional computer aided design package, can readily be converted by the control unit into a connectivity map using conventional computer aided design tools.
In a preferred embodiment the signal processors operate synchronously, each signal processor synchronously cycling through a predetermined number of processing steps. In this case, means can be provided for interfacing the connectivity map to ind
Eastty Peter Charles
Kentish William Edmund Cranstoun
McCulloch Christopher Michael
Cherubin Yveste G
Frommer William S.
Frommer & Lawrence & Haug LLP
Harrison Jessica J.
Smid Dennis M.
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