Pulse or digital communications – Repeaters
Reexamination Certificate
2000-09-08
2001-08-28
Vo, Don N. (Department: 2631)
Pulse or digital communications
Repeaters
C375S220000, C375S377000, C455S557000, C370S420000, C379S442000
Reexamination Certificate
active
06282235
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal processing apparatus. More specifically, the invention relates to a signal processing apparatus such as a terminal interface (DTE (data terminal equipment)—DCE (data circuit equipment) interface) used for a private high-speed modem and the like, or to a system which executes complex processing requiring a decreased number of bits in the input signals and a decreased number of bits for registers that are essentially required, such as a private high-speed data transfer apparatus using a modem, a high-speed data transfer apparatus for CATV network using a band compression system, a digital VTR and a magnetic disk apparatus.
An apparatus for supporting high-speed data requires connectors V.35/X.21 in addition to a connector V.28 recommended by ITU-T (International Telecommunication Union—Telecommunication Recommendation).
Therefore, a private high-speed modem must be equipped with the above-mentioned three kinds of connectors. That is, use of the connectors of different kinds requires three times as many instruments for maintenance as in the case in which the same kinds of connectors are usually used, and the cost for property management regarding these different kinds of connectors increases to three times as much as usual.
In these systems, it is required to collectively execute maintenance at one time in a more simplified manner in order to realize high-speed and complex signal processing at the reduced cost.
2. Description of the Related Art
In a conventional signal processing apparatus which uses several kinds of physically different connectors, signal processing functions must be separately provided by being connected to these connectors.
That is, in the conventional signal processing apparatus, the signal processing functions required by the system are separately realized by hardware, which causes problems in that the number of electric components increases and a production cost of the apparatus increases with an increase in the signal processing functions and that the quality of the signals processed by the apparatus decreases. Besides, the speed of signal processing decreases with an increase in the number of electric components.
In order to clarify the problems inherent in the conventional signal processing apparatus, described below with reference to
FIG. 1
is the constitution of a terminal interface which is related to the conventional signal processing apparatus.
According to the prior art as shown in
FIG. 1
, the terminal interface possesses connectors
90
1
to
90
3
in a number equal to the number of a plurality of channels that connect to plural kinds of data terminal equipment that operates under different interface conditions and driver/receiver units
91
1
to
91
3
in a number equal to the number of a plurality of channels to convert levels of transmission and reception signals, the driver/receiver units
91
1
to
91
3
being connected to separate communication circuits.
Moreover, each communication circuit is provided with a modem for each terminal equipment.
In a conventional terminal interface related to the thus constituted signal processing apparatus, separate communication circuits and modems have been provided and connected for plural kinds of data terminal equipment that operates under different interface conditions.
When the kinds of the apparatus are to be increased, therefore, related devices such as facilities of separate circuits and switches must be newly provided resulting in an increase in the cost.
SUMMARY OF THE INVENTION
The present invention was accomplished in view of the above-mentioned problems, and its main object is to greatly reduce the cost of a system (which is not limited to a field of data transmission only) which executes complex processing yet requires a reduced number of bits in each input signal and a reduced number of bits for registers that are essentially required by reducing the amount of signal processing and the number of electric components, to greatly improve the quality of the apparatus accompanying the reduction in the number of electric components, and to cheaply increase the signal processing functions without decreasing the processing speed.
Another object of the present invention is to provide a terminal interface which enables data terminal equipment that allows a plurality of different interface conditions to be connected to a shared circuit without requiring any related device such as a circuit or a switch, contributes to reducing the size and cost of the apparatus without the need of developing any related device, and makes it easy to increase the kinds of the devices having various interface conditions at the reduced cost. In order to accomplish the above-mentioned objects, the present invention provides a signal processing apparatus comprising a register unit having a number of bits required for the processing that is not greater than a predetermined number of bits, and a ROM which inputs, as an address signal, an output signal from the register unit or an input signal to the signal processing apparatus, and uses an input signal to the register unit as a part of an output signal from the ROM.
Preferably, the signal processing apparatus of the present invention comprises an input signal latch circuit for holding an input signal to the signal processing apparatus in response to a system clock, and an output signal latch circuit for holding an output signal from the ROM in response to a system clock.
More preferably, the signal processing apparatus of the present invention comprises an input signal latch circuit for holding an input signal to the signal processing apparatus in response to a system clock, a selecting circuit for selecting an address signal to the ROM out of a plurality of input signals to the signal processing apparatus in response to a selection signal, and an output signal latch circuit for holding an output signal from the ROM in response to the system clock when the address signal is selected by the selection signal.
Moreover, the signal processing apparatus of the present invention, including a terminal interface, comprises connectors of a number equal to the number of a plurality of channels that connect to plural kinds of data terminal equipment which operates under different interface conditions, level conversion units of a number equal to the number of a plurality of channels that are connected to the connectors to convert levels of the transmission and reception signals, and a DC branching unit that is connected to the level conversion units and has a DC branching function for the plurality of channels, wherein connection is controlled between the data terminal equipment and circuit end equipment provided at a data circuit side, by the DC branching unit.
In the signal processing apparatus of the present invention, an input signal is input to the signal processing apparatus as an address signal of the ROM. Then, the data stored in a memory region designated by the address signal is output from the ROM, and a part of the output signal from the ROM is output to the system and is used as an output signal of the system, and another part thereof or the whole of the remaining part thereof is used as an input signal to the register unit that is essentially required.
Therefore, the address value designating the ROM is expanded, I/O is expanded, and the memory region of ROM is efficiently utilized without waste.
Accordingly, it is possible to greatly reduce the cost of a system which executes a complex process yet requires a reduced number of bits in each input signal and the reduced number of bits for the registers that are essentially required by reducing the amount for signal processing and the number of electric components, to greatly improve the quality of the apparatus accompanying the reduction in the number of electric components, and to cheaply increase the signal processing functions without decreasing the processing speed.
When the signal processing apparatus of the present inventio
Kaku Takashi
Kihara Yasuhide
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Vo Don N.
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