Signal processing

Details Signal processing Signal processing

1998-11-20

2002-04-09

Pham, Chi (Department: 2631)

Pulse or digital communications

Apparatus convertible to analog

C341S122000, C341S123000, C341S143000, C341S155000

Reexamination Certificate

active

06370186

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to a method and a device for signal processing, and in particular to the sampling of analog signals.
DESCRIPTION OF RELATED ART
When sampling an analog signal, for example when converting an analog speech signal to a digital signal, it is convenient to be able to select the frequency of a master clock which controls the sampler to be an integer multiple of the sample rate of the digital signal. However, in the case of, for example, a dual mode cellular phone, which needs to be able to sample analog signals in order to achieve two distinct symbol rates for use in the two modes, it is also advantageous to be able to provide only one master clock frequency generator. If so, it is usually the case that, if one of the sampling rates is an integer fraction of the master clock frequency, then the other is not an integer fraction.
WO96/16482 describes an analog-to-digital converter in which an analog signal is sampled at a rate which is a non-integer fraction of the master clock frequency. Specifically, the analog-to-digital converter includes a sigma-delta modulator for varying the temporal spacing between digital samples. In particular, the delta-sigma modulator is used to generate a jitter sequence, in accordance with which the gap between adjacent digital samples is controlled between two chosen values. The average gap between adjacent samples is the inverse of the sampling rate which is achieved, and the delta-sigma modulator is used to generate a jitter sequence in which the sampling noise, namely the difference between this output sampling and true sampling at the desired sample rate, is hopefully minimised.
However, the requirement to incorporate a delta-sigma modulator in the device adds complication thereto, and increases the power consumption thereof, while fixing the jitter sequence to that generated by the delta-sigma modulator.
SUMMARY OF THE INVENTION
In accordance with the invention, the jitter sequence, in accordance with which the analog signal is sampled, is calculated off-line, and stored in a memory within the device.
This has the advantage that the device itself is simpler and has a lower power consumption.
Preferably, the memory is reprogrammable. This has the advantage that the jitter sequence can be replaced at any time if an improved sequence is devised.
In accordance with one preferred aspect of the invention, there is provided a sampling circuit, including a memory for storing a sequence of values, the gap between adjacent samples being controlled by the sequence.
In accordance with a second aspect of the invention, there is provided a method of sampling a signal, the method comprising sampling the signal at a plurality of points in time, each point being separated from the next by an integer number of cycles at the clock frequency, and the number of cycles separating successive samples forming a sequence, the sequence being pre-calculated and stored.
In accordance with a further aspect of the invention, there is provided a dual mode telephone in which, in one mode, the incoming signal is sampled at a non-integer fraction of a clock frequency, using a jitter sequence to control the sampling.


REFERENCES:
patent: 5610559 (1997-03-01), Dent
patent: 5619202 (1997-04-01), Wilson et al.
patent: 5708432 (1998-01-01), Reynolds et al.
patent: 6147632 (2000-11-01), Iwasaki
patent: 3521288 (1986-12-01), None
patent: 0 019 412 (1980-11-01), None
patent: WO 96/16482 (1996-05-01), None
Johnson, M.J.:A Simple Technique for Fractional Digital Division, Motorola Technical Developments, vol. 112, Oct., 1990, pgs. 3-4.

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