Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system
Reexamination Certificate
1998-07-22
2001-07-10
Shah, Kamini (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Electrical signal parameter measurement system
C702S057000, C702S189000
Reexamination Certificate
active
06259997
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a signal power detection apparatus, and is suitably applied to a received power detection circuit mounted on a portable telephone, for example.
2. Description of the Related Art
Heretofore, portable telephones are able to adjust a received signal to a desired power by controlling a gain of a variable-gain amplifier based on a detected result of a received power with a received power detection circuit. Thus, portable telephones can perform demodulation while keeping a received signal at a constant signal level even when the received signal is affected by fading or the like through a transmission line.
The received power detection circuit will be concretely described below with reference to FIG.
1
. In the following description, assume that a received signal has QPSK (Quadrature Phase Shift Keying) modulation. As shown in
FIG. 1
, in a received power detection circuit
1
, in-phase signal data DI (hereinafter simply referred to as “I data”) and quadrature signal data DQ (hereinafter simply referred to as “Q data”) which are demodulated from the received signal are respectively inputted to latch circuits
2
and
3
. The I data DI and the Q data DQ are generated by analog-to-digital-converting the in-phase signal and the quadrature signal which result from quadrature-demodulating the received signal.
The latch circuits
2
and
3
include clock input terminals CLK to latch a master clock CK
1
of a portable telephone or a clock CK
2
which results from dividing the master clock CK
1
by a frequency divider
4
. The latch circuits
2
and
3
use the clock CK
1
or CK
2
as a sampling clock, latch the I data DI or the Q data DQ inputted to data input terminals IN with sampling based on the clock CK
1
or CK
2
, and output the I data DI or the Q data DQ via data output terminals OUT to squaring circuits
5
and
6
as latch outputs DI
1
and DQ
1
.
The squaring circuit
5
computes a power PI
1
of the I data DI by squaring a voltage value of the latch output DI
1
and outputs the computed power PI
1
to an adder
7
. In the same way, the squaring circuit
6
computes a power PQ
1
of the Q data DQ by squaring a voltage value of the latch output DQ
1
and outputs the computed power PQ
1
to the adder
7
. The adder
7
computes a synthesized power P
1
by adding these powers PI
1
and PQ
1
, and outputs the synthesized power P
1
to a multiplier
8
. The multiplier
8
multiplies the synthesized power P
1
with a predetermined coefficient k in order to prevent a circuit of the succeeding stage from an overflow, and then outputs a resultant received power P
2
to an output latch circuit
9
.
The master clock CK
1
or the clock CK
2
is inputted to a clock input terminal CLK of the latch circuit
9
as well. The latch circuit
9
latches the received power P
2
inputted to a data input terminal IN based on the clock CK
1
or CK
2
, and outputs the latched received power P
2
as a received power value P
3
from a data output terminal OUT. In this manner, this received power detection circuit
1
latches the inputted I data DI and Q data DQ based on the predetermined clock CK
1
or CK
2
, calculates the powers PI
1
, PQ
1
of the respective data by squaring the voltage values, and computes the received power value P
3
by adding the powers PI
1
and PQ
1
.
The conventional received power detection circuit
1
, however, is unable to detect a power at a high accuracy with a low power consumption. This problem will be described with reference to the following concrete examples. Initially, assume that a clock frequency of the master clock CK
1
, for example, is four times as high as the symbol frequency of the I data DI and the Q data DQ. In case that such master clock CK
1
is not frequency-divided and used as a sampling clock, then, a sampling-timing relationship between the master clock and the I data DI or the Q data DQ is presented as shown in
FIGS. 2A and 2D
. That is, in this case, the sampling is performed four times at one symbol period, and is performed at a relatively short interval compared to the symbol period, so that the accurate received power value P
3
can be obtained. However, in this case, since the frequency of the sampling clock is high, the latch circuits
2
,
3
and
9
of the circuit arrangement of CMOS system and the squaring circuits
5
and
6
have to be operated at a high speed so that a power consumption on the received power detection circuit
1
increases as a whole.
On the other hand, in case that the clock CK
2
is obtained by frequency-dividing the master clock CK
1
by four and is used as a sampling clock, the period of which becomes equal to the symbol period, then, a sampling-timing relationship between the sampling clock and the data is presented as shown in
FIGS. 2A and 2B
. That is, in this case, the sampling is performed once at one symbol period and the operation speeds of the latch circuits
2
,
3
and
9
and the squaring circuits
5
and
6
decrease, so that a power consumption on the received power detection circuit can be reduced as compared with the case in which the master clock CK
1
is used as the sampling clock.
In case that the clock CK
2
is obtained by frequency-dividing the master clock CK
1
by eight and is used as a sampling clock, the period of which becomes twice as long as the symbol period, and then, a sampling-timing relationship between the sampling clock and the data is presented as shown in
FIGS. 2A and 2C
. That is, in this case, the sampling is performed once every two symbol periods and the operation speeds of the latch circuits
2
,
3
and
9
and the squaring circuits
5
and
6
further decrease, so that the power consumption on the received power detection circuit can be further reduced.
In this connection, the power consumption on the received power detection circuit can be reduced when the clock CK
2
which results from frequency-dividing the master clock CK
1
is used as the sampling clock. On the contrary, it is impossible to compute the received power value P
3
accurately. An inaccuracy of the received power value P
3
occurs due to a phase relationship between the symbol period and the sampling clock. As shown in
FIG. 2B
, for example, even though the clock CK
2
being equal to the symbol period is generated, the symbol period and the clock CK
2
do not always keep in the same phase relationship, and the phase relationship becomes random depending upon the timing at which the clock CK
2
is generated. The leading edge of the clock CK
2
may occasionally agree with the symbol period as shown in
FIG. 2B
, or the leading edge of the clock CK
2
may occasionally be deviated from the symbol period by a half period as shown in FIG.
2
E.
In this case, fundamentally, when the phase relationship shown in
FIG. 2B
takes place, this phase relationship should be maintained so that the leading edge of the clock CK
2
should constantly agree with the symbol period. In case that the sampling is performed at the leading edge of the clock CK
2
, a narrow phase portion (portion where voltage amplitude is small) of the eye pattern is sampled every time, so that a received power value P
3
relatively smaller than the actual received power value is computed.
On the other hand, in the case where the phase relationship shown in
FIG. 2E
takes place, the leading edge of the clock CK
2
should constantly agree with the center of the symbol period, so that a wide phase portion (portion where voltage amplitude is large) of the eye pattern is sampled every time. As a consequence, a received power value P
3
relatively larger than the actual received power value is computed.
When the clock CK
2
which results from frequency-dividing the master clock CK
1
by 4 is used as the sampling clock, there is the problem that the received power value P
3
cannot be computed accurately. This problem is found also when the clock CK
2
which results from frequency-dividing the master clock CK
1
by 8 is used as the sampling clock.
When the clock CK
2
equal
Iwasaki Jun
Konya Satoshi
Sasho Noboru
Yamaura Tomoya
Barbee Manuel L.
Maioli Jay H.
Shah Kamini
Sony Corporation
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