Signal phasing arrangement in a system for doubling the digital

Details Signal phasing arrangement in a system for doubling the digital Signal phasing arrangement in a system for doubling the digital

1991-04-29

1994-06-14

Chin, Stephen

Pulse or digital communications

Spread spectrum

Direct sequence

375118, H04B 710, H04L 102, H04L 700, H04L 2536

Patent

active

053217276

ABSTRACT:
In response to a low-frequency superframe signal, the input frames TRA, TRB of each of two digital channels, shifted in time, are applied each to a frame locking circuit which produces sync signals SYA, SYB; and are also applied to a common cyclic addressing double memory. In the write mode each memory location is addressed to contain a block of TRA and a block of TRB of the same rank controlled by write counters which are incremented by the signals SYA and SYB. Each location has a read counter which is shifted to the more delayed signal of the sync signals SYA and SYB by a phase comparator and a coincidence detector. The output signals having information frames TRA' and TRB' are in phase.

REFERENCES:
patent: 3628149 (1971-12-01), Swan
patent: 4015205 (1977-03-01), Ikeda et al.
patent: 4218654 (1980-08-01), Ogawa et al.

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