Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input
Reexamination Certificate
2002-03-22
2003-07-01
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Phase shift by less than period of input
C327S234000, C327S236000, C327S007000
Reexamination Certificate
active
06586983
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device to transfer data between a plurality of devices that utilize high frequency. More specifically, the present invention is related to a phase adjustment device that realizes data transmission by adjusting the clock phase of a reception side device, and to an adjustment mechanism that makes the optimum clock phase adjustment. The present invention may, for example, be utilized in communications between processors in multiprocessor systems.
2. Description of the Related Art
Conventional signal transmission systems are disclosed in, for example, Japanese Unexamined Patent Publication No. H11-136312 and Japanese Unexamined Patent Publication No. H11-112483.
FIG. 2
illustrates the signal transmission system disclosed in Japanese Unexamined Patent Publication No. H11-136312. As shown in
FIG. 2
, the signal transmission system includes a transmission side device
20
and a reception side device
30
which operate synchronously by the same clock generator
51
. The transmission side device
20
includes a transmission side pattern generator
21
that generates a signal having a specified pattern in order for the reception side device
30
to determine whether or not the transmission synchronization is correct. The signal having a specified pattern generated by the pattern generator
21
is supplied to output flip-flops
22
, which are provided corresponding to each signal line transmitted on a transmission route
10
. Pattern signals transmitted to the transmission route
10
are received by the reception side device
30
and are input into input flip-flops
33
corresponding to each signal line. The clock signal transmitted from the clock generator
51
undergoes phase modification by a sampling phase adjustment circuit
31
, and is input to the flip-flops
33
as a clock signal that causes the operation of the input flip-flops
33
. A control unit
52
generates a phase adjustment signal
41
to designate an amount of modification for phase modification.
The reception side device
30
includes a pattern generator
35
. The pattern generator
35
generates the same pattern signal as the pattern generator
21
of the transmission side device
20
. The signal having a specified pattern generated by the pattern generator
35
passes through a delay circuit
38
and is input to a comparator
39
. The signals output from the input flip-flops
33
pass through respective flip-flops
34
for synchronization and are input to the comparator
39
. The signals pass through the synchronization flip-flops
34
because there is the high possibility that the operational clock of the input flip-flops
33
is not synchronized with the operational clock inside the reception side device
30
. The synchronization flip-flops
34
are provided to heighten circuit stability and for the comparator
39
to conduct reliable comparisons.
The control unit
52
attempts to synchronize the data transmission by providing an amount of signal delay based on the transmission route
10
, and by designating an amount of phase modification that matches the amount of delay to the sampling phase adjustment circuit
31
. Information indicating whether or not the two input signals input to the comparator
39
agree is transmitted from the comparator
39
to the control unit
52
. The control unit
52
can use this information to determine whether or not the reception side device
30
as a whole is operating normally in relation to the transmission of data signals.
FIG. 3
illustrates the signal transmission system described in Japanese Unexamined Patent Publication No. H11-112483. As shown in
FIG. 3
, a transmission side device
60
and a reception side device
70
operate synchronously with the same clock
51
. The transmission side device
60
includes a pattern generator
61
that transmits test patterns for synchronization adjustment to the reception side device
70
to adjust the phase discrepancy between a plurality of signals transmitted by a transmission route
10
and the test pattern for phase adjustment, which is conducted to adjust the clock phase of the transmitted signal.
A signal having a specified pattern is generated by the pattern generator
61
and supplied to output flip-flops
22
that are provided corresponding to the plurality of signals transmitted by the transmission route
10
. The pattern signals transmitted by the transmission route
10
are received by the reception side device
70
, and are input into respective sampling signal phase adjustment circuits
76
for every signal line. The sampling signal phase adjustment circuits
76
change the sampling phase according to an adjustment signal designated by a control unit
72
. The signals that are output from the respective sampling signal phase adjustment circuits
76
are respectively input into synchronization adjustment circuits
73
.
The control unit
72
controls the synchronization adjustment circuits
73
, and the amount of transmission delay for each signal line is controlled and input into a reception determination circuit
75
. The reception determination circuit
75
detects the delay time discrepancy between signal lines by using the test pattern for phase adjustment to determine whether or not all of the plurality of input signals are the same. Moreover, the reception determination circuit
75
detects the phase shift delay of the transmission route by determining whether or not the received signal is the same as the test pattern for synchronization adjustment. From the results of the above detection, the control unit
72
designates the amount of adjustment to the signal phase adjustment circuit
76
and the synchronization adjustment circuit
73
in order that the reception side device
70
can receive signals normally.
At present, if a device having a low operational frequency must be utilized, when communicating between devices, there is no problem with the signal delay becoming hidden in the clock gap, even if using simple adjustment circuits such as the conventional adjustment circuits. However, in order to notably improve operational frequency, future information processing devices will have significant problems with the delay of signals and the amount of delay between signals, even when transmitting slight distances like those between neighboring circuit boards. Moreover, it is expected that this problem will become even more pronounced in the future as the operational frequencies of processors improve.
Specifically, structural errors during manufacture, such as variations in materials and valid line lengths, or fluctuation errors caused by changes of environmental conditions, such as the temperature and humidity of the signal lines, are the cause of: (1) transmitted signals fluctuating in conjunction with the passage of time; and (2) signal fluctuations causing fluctuation in the amount of phase modification necessary for the reception side device to receive signals normally. It is not possible to have normal signal reception locally when the phase is on the boundary of the transmission cycle, when a specific phase has great noise, or when a phase cannot fulfill the timing restriction for signal transmission from a circuit that is operating according to one clock signal to a circuit that is operating according to another clock signal.
FIG. 4A
illustrates a range of what is conventionally considered to be the transmittable amount of phase modification. More particularly, the horizontal axis in
FIG. 4
indicates the amount of phase modification, and, the further to the right along the horizontal axis in
FIG. 4
, the greater the amount of phase modification. As shown in
FIG. 4A
, point A is a point at which the amount of phase modification is zero (0), specifically, the point at which no reception signal phase modification is conducted, and point B is a point at which the amount of phase modification becomes one (1) cycle. As shown in
FIG. 4A
, the range of the dashed lines enclosed by the elliptical framework corresponds to t
Shimizu Toshiyuki
Tsuiki Jun
Callahan Timothy P.
Fujitsu Limited
Luu An T.
Staas & Halsey , LLP
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