Signal output system

Details Signal output system Signal output system

1999-09-23

2002-11-26

Corrielus, Jean (Department: 2631)

Pulse or digital communications

Cable systems and components

C333S032000, C330S144000

Reexamination Certificate

active

06487250

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal output circuit for outputting signals to the transmission line, especially to a signal output system by which, for instance, a waveform distortion on the signal line caused by a high-speed signaling can be suppressed.
2. Description of the Related Arts
FIG. 17
shows the semiconductor integrated circuit with output impedance self correction circuit disclosed in Unexamined Japanese Patent Publication No. 10-261948.
In the semiconductor integrated circuit with output impedance self correction circuit of
FIG. 17
, an internal circuit
105
of a semiconductor integrated circuit
107
is connected to an output circuit
101
, and an output terminal
102
is connected to a receiving circuit
108
via a transmission line
109
having an impedance, such as a cable or a print wiring board. According to this conventional art, the input to the receiving circuit
108
needs no termination process, and the input impedance is supposed to be infinite.
The initial state of the output circuit
101
, in this conventional art, is set to have the maximum output impedance, meaning the minimum drive ability, at the time just after the power-on of the semiconductor integrated circuit
107
. Then, the output impedance is going to be sequentially adjusted.
The internal circuit
105
transmits a test pattern signal to the output circuit
101
in order that the output terminal
102
may repeatedly output a signal of low level and a signal of high level, meaning Low level→High level→Low level→High level.
When the output signal begins the transition from Low level to High level, an initial amplitude voltage output from the output circuit
101
is detected at a specific sampling timing by using an output voltage detecting circuit
103
. Then, until the detected initial amplitude voltage is found to be around the half of the maximum output amplitude value, meaning until the output impedance is found to be equal to the impedance of the transmission line
109
, the sampling test is repeated by way of changing the output impedance of the output circuit
101
, at an impedance control signal generating circuit
101
.
The value of the output impedance at the time of becoming equal to that of the transmission line
109
is stored in the impedance control signal generating circuit
104
. Then, when a signal is output from the output circuit
101
, the output impedance of the output circuit
101
is controlled to be the above value.
FIG. 18
shows signal waveforms according to the above conventional art. An output-terminal-waveform
110
indicates a signal waveform at the output terminal
102
of
FIG. 17. A
receiving-circuit-input-waveform
111
indicates a signal waveform at the input terminal (not shown) of the receiving circuit
108
.
Though an output signal from the output terminal
101
is reflected at the receiving circuit
108
, the output signal is not re-reflected at the output terminal
102
because the output impedance of the: output circuit
101
is matched with the characteristic impedance of the transmission line
109
. Consequently, useless ringing is not generated.
The followings are problems of the conventional signal output system, resulted from the above-stated configuration.
FIG. 19
shows a general bus line. Each of devices No.
2
through No.
5
, that is
202
through
205
, is connected to a bus line
207
via a branch line
208
. Each of the bus lines
207
and the branch lines
208
has the characteristic impedance of 50&OHgr; and the length of 5 cm.
In
FIG. 19
, when the above buffer is applied to each of the devices, the output impedance is automatically adjusted to be around 50&OHgr;.
FIG. 20
shows a simulation result of input waveforms of the No.
2
device
202
and the No.
6
device
206
, simulated by using a circuit simulator (SPICE), in the case of the No.
1
device
201
outputting signals which are periodically varied in the toggling state in 200 MHz (5 nsec) cycle. In
FIG. 20
, the waveform in a solid line denotes the input waveform to the No.
2
device
202
and the waveform in a broken line denotes the input waveform to the No.
6
device
206
. A signal at the device, such as No.
2
device
202
, closer connected to the output driver (in this case, No.
1
device
201
) rises later than other devices far connected to the output terminal, because of the reflection effect. In
FIG. 20
case, only about 700 psec is kept as a time for performing the setup.
Consequently, the above defect based on the conventional art principle as shown in
FIG. 17
makes the high-speed transmission difficult and enormously restricts the degree of freedom of circuit design.
SUMMARY OF THE INVENTION
In view of the foregoing, it is one of objects of the present invention to provide a signal output system in which a wave distortion generated in the high-speed signal transmission is suppressed and the bus operation speed is enhanced, by way of dynamically controlling an output impedance at the beginning of a signal transmission in order to change the output impedance to high from low.
It is another object of the present invention to provide a signal output system in which an output current is suppressed by changing the output impedance from low to high at the beginning of a signal transmission.
It is another object of the present invention to provide a signal output system in which the degree of freedom of circuit design is not restricted because, as stated above, a wave distortion generated in the high-speed signal transmission can be suppressed.
According to one aspect of the present invention, a digital signal output circuit for outputting an output signal to a signal line via an output buffer comprises
an output impedance changing part, connected between the output buffer and the signal line, for changing an output impedance,
an output-signal-state-change detector for detecting a change of the output signal, and
a continuous-change performing part for controlling the output impedance changing part, at a changing timing of the output signal, so as to continuously change the output impedance, when the output-signal-state-change detector detects the change of the output signal.
According to another aspect of the present invention, in the digital signal output circuit, the continuous-change performing part controls the output impedance changing part, at the changing timing of the output signal, so as to continuously change the output impedance from low to high, when the output-signal-state-change detector detects the change of the output signal.
The above and other objects, features, and advantages of the invention will be more apparent from the following description when taken in connection with the accompanying drawings.


REFERENCES:
patent: 5880635 (1999-03-01), Satoh
patent: 07202671 (1995-08-01), None
patent: 10261948 (1997-03-01), None
patent: 10105304 (1997-08-01), None
patent: 2000276251 (2000-10-01), None
AVC Logic Family Technology and Applications (Texas Instrument, Aug. 1998).
Dynamic Output Control (DOC TM) Circuitry Technology and Application (Texas Instrument, Aug. 1998).

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