Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Slope control of leading or trailing edge of rectangular or...
Reexamination Certificate
2001-01-31
2002-08-06
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Slope control of leading or trailing edge of rectangular or...
C327S172000
Reexamination Certificate
active
06429708
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a signal sending system and method that can set a plurality of different data transfer rates and that conforms to an interface standard such as AT Attachment (ATA) or Small Computer System Interface (SCSI). This system and method enables a signal to be sent from a signal output device to a signal receiving device via a signal sending line at a predetermined data transfer rate.
2. Description of the Related Art
A signal sending system with the ability to set a plurality of different data transfer rates and enable a signal to be sent from a signal output device to a signal receiving device via a signal sending line at a predetermined data transfer rate can be used with such peripheral devices as a hard disk drive (HDD), and a CD-ROM drive in a computer system.
Some interface standards used between a signal output (host system) and signal receiving (peripheral) devices in a signal sending system as the one described above include the ATA interface and the SCSI. Those standard interfaces, which include the legacy ATA interface and the Ultra ATA/66 interface, contain a plurality of different interface standards to account for various data transfer procedures and data transfer rates. Also, there are two types of sending cables used for the connection between the output and receiving devices.
The legacy ATA interface supports all the data transfer rates in the PIO data transfer mode and all the data transfer rates in the multi-word DMA data transfer mode. The Ultra ATA/33 interface supports data transfer rates up to 33.3 MB/s of the Ultra DMA data transfer mode. It also allows higher transfer rate interfaces to maintain backward compatibility to the older legacy ATA interface. The Ultra ATA/66 interface supports data transfer rates up to 66.6 MB/s of the Ultra DMA data transfer mode while it enables the Ultra ATA/33 interface to keep its compatibility with higher transfer rate interfaces. Consequently, a signal sending system conforming to the Ultra ATA/66 interface must be able to send signals at 9 types of data transfer rates from 3.3 MB/s to 66.6 MB/s.
The aforementioned ATA interface sends 16-bit parallel data, using 16 data buses. A signal sending system which conforms to the ATA interface uses a flat 40C cable which consists of 40 signal lines (data signal, control signal, and ground lines) or a flat 80C cable, which has 80 signal lines. The 40C cable includes 16 data signal lines placed in parallel. And, because the potentials of those 16 data signal lines are changed simultaneously due to a simultaneous switching by the driver circuit of the signal output device, crosstalk is apt to be generated at a high data transfer rate. To remedy this problem, a ground line is inserted between signal lines in the 80C cable.
Signal integrity is defined as the accuracy of the data/strobe signal between a host system and a peripheral device. The strobe signal is assumed to be the timing reference for latching the data signal. If a latch timing is disturbed and/or a data signal level is changed by a generated noise, a data transfer error occurs, and the signal integrity is considered low. High signal integrity denotes high accuracy of the data/strobe signal between the host system and the peripheral.
Each peripheral and the host system has its own signal I/O device. The signal I/O devices are used to exchange data between the host system and each of the peripherals. A signal I/O device at the data transfer side is used as a signal output device and a signal I/O device at the data receiving side is used as a signal receiving device. Drive circuit signal output devices are used to output signals to signal lines. The drive circuit can output a signal with electrical properties common to all the possible data transfer rates and all the usable cable types (40C and 80C cables).
SUMMARY OF THE INVENTION
The signal output device of the present invention is able to set a plurality of different data transfer rates and output a signal to a signal receiving device via a signal sending line at a predetermined data transfer rate. The signal output device consists of a driver circuit which can set a plurality of different slew rates and output the signal to the signal sending line at a predetermined slew rate, and a controller that sets a slew rate of the driver circuit according to the predetermined data transfer rate.
The signal sending method of the present invention sets any one of a plurality of the different sending rates, thereby enabling a signal to be sent to a signal receiving device from a signal output device via a signal sending line at the predetermined data transfer rate. When a driver circuit is included with the above mentioned signal output device, the driver circuit can set a plurality of different slew rates and output the signal to the signal sending line at a predetermined slew rate. A controller is also included in the signal output device to set a slew rate of the driver circuit according to the predetermined data transfer rate. The signal transmission method includes the following steps:
setting a slew rate of the driver circuit to a standard value that is in accordance with the predetermined data transfer rate, thereby starting signal transmission;
determining whether or not the data transfer error occurrence rate is below a predetermined allowable threshold. This threshold is the data transfer error occurrence being caused by a signal sent to the signal receiving device from the driver circuit;
changing the slew rate of the driver circuit if the data transfer error occurrence rate is determined to be over the allowable threshold Eth;
searching for a slew rate value that can decrease the data transfer error occurrence rate below the allowable threshold or decrease the data transfer error occurrence rate;
setting the slew rate value as a new standard value; and
setting the new standard slew rate for the driver circuit if the slew rate value can decrease the data transfer error occurrence rate below the allowable threshold or decrease the data transfer error occurrence rate.
REFERENCES:
patent: 5559452 (1996-09-01), Saito
patent: 6005890 (1999-12-01), Clow et al.
patent: 6047346 (2000-04-01), Lau et al.
patent: 6069504 (2000-05-01), Keeth
patent: 6141263 (2000-10-01), Protzman
patent: 6194935 (2001-02-01), Pioppo et al.
Asano Hideo
Oshikawa Hiroshi
Sakai Tatsuya
Sato Masahiko
Bracewell & Patterson L.L.P.
Cox Cassandra
Lam Tuan T.
Raissinia Abdy
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