Signal multiplexing circuit

Details Signal multiplexing circuit Signal multiplexing circuit

1999-01-15

2002-05-07

Patel, Ajit (Department: 2662)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C327S407000

Reexamination Certificate

active

06385214

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal multiplexing circuit which successively selects and sends out one by one ensured multi-phase differential data from among multi-phase differential data which become ensured for a certain period after changing in different phases.
2. Description of the Related Art
FIG. 6
is a circuit diagram of an example of the configuration of a signal multiplexing circuit of the related art.
This signal multiplexing circuit
10
comprises signal extracting circuits
11
-
1
,
11
-
2
,
11
-
3
, . . .
11
-n constituted by differential amplifiers, a selector
12
, an output circuit
13
, and a pair of signal lines Q and QB (B indicates inversion) taking the wired-OR of the outputs of the signal extracting circuits
11
-
1
to
11
-n and inputting the same to the output circuit
13
.
The signal extracting circuit
11
-
1
comprises n-channel MOS (NMOS) transistors NT
11
and NT
12
whose sources are connected to each other.
A connection point of the sources of the NMOS transistors NT
11
and NT
12
is connected to an output
12
-
1
of the selector
12
.
A gate electrode of the NMOS transistor NT
11
is connected to an input line of the differential data signal IN
1
and a drain thereof is connected to the signal line QB. A gate electrode of the NMOS transistor NT
12
is connected to an input line of the differential data signal IN
1
B and a drain thereof is connected to the signal line Q.
Below, in the same way, the signal extracting circuit
11
-n comprises NMOS transistors NTn
1
and NTn
2
whose sources are connected to each other.
A connection point of the sources of the NMOS transistors NTn
1
and NTn
2
is connected to an output
12
-n of the selector
12
.
A gate electrode of the NMOS transistor NTn
1
is connected to an input line of the differential data signal INn and a drain thereof is connected to the signal line QB. A gate electrode of the NMOS transistor NTn
2
is connected to an input line of the differential data signal INnB and a drain thereof is connected to the signal line Q.
The selector
12
has n number of select lines
12
-
1
to
12
-n which are respectively connected to the connecting points of sources of the NMOS transistors of the signal extracting circuits
11
-
1
to
11
-n. It selectively drives (passes a current to) the respective select lines
12
-
1
to
12
-n and makes the signal extracting circuits
11
-
1
to
11
-n operate as differential amplifiers.
The output circuit
13
comprises npn-type transistors T
131
and T
132
and resistors R
131
and R
132
.
An emitter of the transistor T
131
is connected to the signal line Q, and an emitter of the transistor T
132
is connected to the signal line QB.
A signal OUT is output from a collector of the transistor T
131
, and a signal OUTB is output from the collector of the transistor T
132
.
In the above configuration, when multiplexing n-phase data, multi-phase differential data signals IN
1
, IN
1
B to INn, INnB are input to the respective signal extracting circuits
11
-
1
to
11
-n.
Here, the differential data signals are supplied to the gate electrodes of the NMOS transistors NT
11
, NT
12
, . . . NTn
1
, NTn
2
constituting the differential amplifiers of the respective signal extracting circuits
11
-
1
to
11
-n.
Note that the timing is adjusted so as to change a value of an input potential when the signal extracting circuits
11
-
1
to
11
-n are not selected by the selector
12
and not to change the value when selected.
The signal extracting circuits
11
-
1
to
11
-n are selected successively one by one by the selector
12
. As a result, signals are output from the signal extracting circuit in which the input is ensured to the signal lines Q and QB.
The signals output to the signal lines Q and QB are input to the output circuit
13
where multiplexed output signals OUT and OUTB are obtained.
The problem to be solved by the invention is as follows:
In the above-mentioned signal multiplexing circuit of the related art, the input potential of the differential amplifier of the signal extracting circuit inverts when the value of the differential data signal changes. The inversion of the potential causes a noise signal in an output to the output circuit
13
via the parasitic capacitances of the NMOS transistors (for example, NT
11
and NT
12
) constituting the signal extracting circuit.
This noise signal is generated when the signal extracting circuit is not selected by the selector. This ordinarily happens when another extracting circuit is selected and is outputting a signal.
Therefore, the noise signal disturbs the output of other data and causes an increase of jitter of the output.
Here, the relationship of the noise output and the jitter will be explained with reference to FIG.
7
.
An output potential of the output circuit
13
(solid line shown in
FIG. 7
) changes due to an output from a signal extracting circuit (differential amplifier) selected by a selector
12
.
If noise is generated by another output which is not selected at the same time, the actual output potential from the output circuit
13
becomes as shown by the dotted line shown in FIG.
7
. The timing of change of the output becomes earlier by exactly td which causes jitter in the output.
It is necessary to reduce the jitter to operate a multiplexing circuit at a high speed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a signal multiplexing circuit capable of reducing jitter.
To achieve the above object, according to a first aspect of the present invention, there is provided a signal multiplexing circuit which ensures multi-phase differential data changing in different phases to multiplex the same, comprising a plurality of signal extracting circuits, each receiving as input different differential data, including a first circuit for outputting the input differential data when receiving a select drive signal and a second circuit for outputting the input differential data with an inverted phase with respect to the first circuit so as to add it to the output of the first circuit and never being selected by the select drive signal; a driving source for selectively outputting the select drive signal to the first circuits of the signal extracting circuits; and an output circuit for multiplexing outputs of the signal extracting circuits and outputting the same.
According to a second aspect of the invention, there is provided a signal multiplexing circuit which ensures multi-phase differential data changing in different phases to multiplex the same, comprising a plurality of signal extracting circuits, each receiving as input different differential data, including a first circuit for outputting the input differential data when receiving a select drive signal and a second circuit for outputting the input differential data with an inverted phase with respect to the first circuit so as to add it to the output of the first circuit and never being selected by the select drive signal; a selector for selectively outputting the select drive signal to the first circuits of the signal extracting circuits; and an output circuit for multiplexing outputs of the signal extracting circuits and outputting the same.
In the first and second aspects of the invention, preferably the output circuit comprises a pair of first and second signal lines connected in a wired-OR manner to outputs of the first and second circuits of the signal extracting circuits and an output amplifier for outputting the signals which are output to the first and second signal lines.
More preferably, the first circuit comprises first and second transistors with first terminals which are commonly connected; the second circuit comprises third and fourth transistors with first terminals which are commonly connected; one data of the differential data is input to second terminals of the first and fourth transistors, another data of the differential data is input to the second terminals of the second and third transistors, third terminals of the first and third trans

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