Signal-level converter

Details Signal-level converter Signal-level converter

1983-07-08

1986-02-25

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 307270, 307279, 307362, H03K 19094, H03K 3023, H03K 3356, G11C 800

Patent

active

045729743

ABSTRACT:
A signal-level converter for controlling digital MOS circuits, particularly an address-buffer circuit for dynamic MOS memories, is designed in integrable form in MOS technology and is addressed on one hand by a first supply potential and a second supply potential connected as the reference potential, and on the other hand, at a signal input by the digital control signal to be processed, and furthermore includes cross-coupled field-effect transistor pairs as well as two output terminals carrying signals inverted relative to each other for controlling the digital circuit.

REFERENCES:
patent: 4077031 (1978-02-01), Kitagawa et al.
patent: 4130768 (1978-12-01), Bula et al.
patent: 4396845 (1983-08-01), Nakano
patent: 4417163 (1983-11-01), Otsuki et al.
patent: 4441039 (1984-04-01), Schuster
IEEE Journal of Solid-State Circuits, vol. SC-15, No. 3 (10/1980), pp. 843-844.
Furman, "Address Buffer True/Complement Generator", IBM Tech. Disc. Bull.; vol. 18, No. 11, pp. 3597-3598; 4/1976.
Lee et al., "A 80ns 5V-Only Dynamic RAM"; ISSCC 79; Session XII; Dynamic Memories; Digest of Technical Papers 2 pps.; 2/15/1979.

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