Signal level conversion circuit for converting a level of an inp

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control

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Details

326 63, 326 68, H03L 500

Patent

active

055415466

ABSTRACT:
A signal level conversion circuit is constructed with an inverter (103, 104) provided between a voltage source terminal (V2) and ground, first and second enhancement NMOS transistors (101, 107) connected in parallel to each other and provided between a signal input terminal (I) and an input node of an inverter. An enhancement PMOS transistor (102) is provided between the input node of the inverter and the voltage source terminal (V2). Gate electrodes of the first NMOS and the PMOS transistors are connected to an output of the inverter and a gate electrode of the second NMOS transistor (107) is connected to a constant voltage source (V1) of which voltage level is greater than a threshold voltage of the second NMOS transistor (107) and smaller than a sum of an input signal voltage inputted to the input terminal and the threshold voltage of the second NMOS transistor.

REFERENCES:
patent: 3906254 (1975-09-01), Lane et al.
patent: 4080539 (1978-03-01), Stewart
patent: 4571504 (1986-02-01), Iwamoto et al.
patent: 4603264 (1986-07-01), Nakano
patent: 5111076 (1992-05-01), Tarng

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