Signal holding circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

Patent

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Details

307253, 455312, H03K 1760

Patent

active

041985419

ABSTRACT:
A signal holding circuit is disclosed in which a parallel circuit of a constant current source circuit comprising a transistor having a constant voltage supplied to a base thereof and a hold capacitor is connected to an emitter follower transistor, a first control transistor is connected between a base of the emitter follower transistor and ground, a second control transistor is connected between the base of the transistor of the constant current source circuit and ground, and a control pulse corresponding in time to a duration of the pulsive noise is applied to the bases of the first and second control transistors to render the first and second control transistors conductive only during the application of the control pulse so that a charging time constant of the hold capacitor during the conduction of the emitter follower transistor is reduced and a discharging time constant of the hold capacitor during the cutoff of the emitter follower capacitor is increased.

REFERENCES:
patent: 3401359 (1968-09-01), Becker
patent: 3509468 (1970-04-01), Overlie
patent: 3588705 (1971-06-01), Paine
patent: 3659120 (1972-04-01), Saeki
patent: 3952252 (1976-04-01), Cornacchia
patent: 4058804 (1977-11-01), Sawada et al.

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