Signal hold circuit

Details Signal hold circuit Signal hold circuit

2002-03-27

2003-04-01

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S060000, C327S095000, C327S096000

Reexamination Certificate

active

06542009

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to the technical field of signal hold circuits. In particular, the present invention pertains to a peak hold circuit that outputs the signal of a waveform that varies to follow the peak value of a prescribed signal.
BACKGROUND OF THE INVENTION
The Read-channel circuit of an MOD (Magnetic optical disk) has a peak hold circuit that outputs the peak value of an analog signal that increases and decreases periodically.
As shown in
FIG. 4
, a conventional peak hold circuit
101
has comparator
111
, current output circuit
112
and capacitor
113
.
The inverting input terminal (−) of comparator (
111
) is connected to input terminal (
114
). The comparator outputs a comparison signal, to be described later, corresponding to the analog voltage DI input to input terminal (
114
).
Current output circuit (
112
) has switch transistor (
121
), diode (
122
), source-side constant current circuit (
123
), and sink-side constant current circuit (
124
).
The output terminal of comparator (
111
) is connected to the gate terminal of switch transistor (
121
). Switch transistor (
121
) is turned on or off corresponding to the comparison signal output from comparator (
111
). Source-side constant current circuit (
123
) is connected to the terminal of capacitor (
113
) on the high potential side via switch transistor (
121
) and diode (
122
). When switch transistor (
121
) is turned on, a source-side constant current I
1
is supplied to capacitor (
113
).
Sink-side constant current circuit (
124
) is directly connected to the terminal of capacitor (
113
) on the high potential side, while the terminal of capacitor (
113
) on the low potential side is grounded. Sink-side constant current circuit (
124
) always absorbs sink constant current I
2
from capacitor (
113
).
As a result, when switch transistor (
121
) is turned on, capacitor (
113
) is charged by constant current (I
1
−I
2
) as the difference between source constant current I
1
and sink constant current I
2
, and the voltage across capacitor (
113
) rises. On the other hand, when switch transistor (
121
) is turned off, source-side constant current circuit (
123
) is cut off from capacitor (
113
), and capacitor (
113
) is discharged as sink constant current I
2
from capacitor (
113
) is sunk. As a result, the voltage across capacitor (
113
) drops.
The terminal of capacitor (
113
) on the high potential side is connected to output terminal (
115
). The voltage across capacitor (
113
) is output, from output terminal (
115
) as output signal Vout, to an external circuit not shown in the figure.
Output terminal (
115
) is connected to the non-inverting input terminal (+) of comparator (
111
). The aforementioned analog voltage DI and output signal Vout are input to comparator (
111
). Comparator (
111
) compares output signal Vout with analog voltage DI, generates a comparison signal according to the comparison, and outputs the comparison signal to the gate terminal of switch transistor (
121
). The comparison signal is a low-level signal if output signal Vout is lower than analog voltage DI, and becomes a high-level signal if the output signal is higher than the analog voltage.
Switch transistor (
121
) is a P-channel MOS transistor. It will be turned on when the comparison signal is low level, and will be turned off when the comparison signal is high level. As described above, output signal Vout varies such that it drops when output signal Vout is higher but rises when it is lower than analog voltage DI. The amount of rise in output voltage Vout per unit time is determined by constant current (I
1
−I
2
), that is, the difference between source constant current I
1
and sink constant current I
2
. The amount of drop per unit time is determined by sink constant current I
2
.
Analog voltage DI is an AC signal with a prescribed frequency, such as a voice signal. The relationship between analog voltage DI and output signal Vout will be explained with reference to FIG.
5
. With time plotted on the abscissa and voltage on the ordinate, the waveforms of said analog voltage DI and output signal Vout are shown as curves (W) and (X) in
FIG. 5
, respectively.
When output signal Vout is lower than analog voltage DI and analog voltage DI rises, output signal Vout rises. When analog voltage DI rises and output signal Vout is lower than analog voltage DI at the time when the analog voltage reaches the peak value (symbol t
p
in the figure), analog voltage DI drops after time t
p
when it reaches the peak value. On the other hand, output signal Vout rises. After that, the magnitude relationship between output signal Vout and analog voltage DI is reversed. The reversal time is indicated by t
b
in FIG.
5
.
After time t
b
when the magnitude relationship between output signal Vout and analog voltage DI is reversed, output signal Vout becomes higher than analog voltage DI. Capacitor (
113
) is discharged as sink constant current I
2
from capacitor (
113
) is sunk. As a result, output signal Vout starts to drop. The amount of drop of output signal Vout per unit time is determined by the aforementioned sink constant current I
2
. However, output signal Vout drops more gradually than does analog voltage DI because the sink current I
2
is preset to a small value.
During the period when output signal Vout drops, the AC analog voltage DI first drops and then rises until reaching the peak value. However, depending on the magnitude of the peak value of analog voltage DI, the trace of the voltage value of output signal Vout and the trace of the voltage value of analog voltage DI will or will not cross before analog voltage DI rises to the peak value.
If analog voltage DI has a large peak value and the trace of the voltage value of output signal Vout crosses the trace of the voltage value of analog voltage DI, the magnitude relationship with voltage signal Vout is reversed after the crossing time, and output signal Vout becomes lower than analog voltage DI. Therefore, output signal Vout is able to rise until it becomes higher than analog voltage DI, and reaches a voltage level that is almost the same as the peak value of analog voltage DI.
However, if analog voltage DI has a small peak value and the trace of the voltage value of output signal Vout does not cross the trace of the voltage value of analog voltage DI, for example, as shown by curve (Z) in
FIG. 6
, output signal Vout is still higher than analog voltage DI, but is unable to reach a voltage level that is almost the same as the peak value of analog voltage DI. If the time period during which output voltage Vout is higher than analog voltage DI (T
j
in the figure) is long, the waveform of output signal Vout is unable to draw the correct envelope of the peak value since output signal Vout is not on almost the same voltage level as the peak value of analog voltage DI during that period, as shown by curve (Z) in FIG.
6
.
As described above, since the amount of drop of output signal Vout per unit time is determined by the amount of sink constant current I
2
generated by sink-side constant current circuit (
124
), if the amount of sink constant current I
2
is increased, the amount of drop of output signal Vout per unit time can be increased. Therefore, even if analog voltage DI drops sharply, the output signal Vout is able to drop below analog voltage DI in a relatively short amount of time to match with the peak value. Sink constant current I
2
flows constantly, however. The power consumption will be increased if the amount of sink constant current in constant flow is increased. Also, if the amount of rise or amount of drop of output signal Vout per unit time is increased, the flatness of the waveform of output signal Vout will deteriorate.
One aspect of the present invention is to solve the problem of the aforementioned conventional technology by providing a technology, such as a peak hold circuit, that can obtain and output peak value correctly to follow the variation in analog voltage.
SUMMARY OF INVENTION
In order

Affiliated with

Also associated with

Rating

Signal hold circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Signal hold circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signal hold circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3092496