Signal generator, and method

Details Signal generator, and method Signal generator, and method

2001-02-16

2002-04-30

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C331S00100A, C331S016000, C327S156000, C327S291000, C327S299000

Reexamination Certificate

active

06380811

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to an arrangement that generates periodic electrical signals, and more particularly, to a signal generator for a microprocessor, and to a method.
BACKGROUND OF THE INVENTION
Many applications, such as microprocessors, require a clock having a high frequency. While quartz oscillators operate at a lower frequency, conversion is often required.
FIG. 1
illustrates a simplified block diagram of a phase-locked loop (PLL) circuit. The PLL circuit has a phase comparator (PC), a low pass filter (LPF) with capacitor, and a voltage controlled oscillator (VCO). The PLL circuit provides that the frequency F
OUT
of the output signal Y remains locked to the frequency F
REF
of the input signal X (or to a multiple of F
REF
). The phase comparator detects phase differences between the input signal X and the output signal Y and acts on the VCO to minimize the difference.
It is desired to integrate the complete PLL circuit and the processor into a monolithic integrated chip. For many “on-chip” applications, the input signal X has a low reference frequency (e.g., F
REF
≈32 kHz) and the output signal Y has a very high output frequency (e.g., F
OUT
≈100 . . . 200 MHz). Frequency multiplication is required by a factor F
OUT
/F
REF
of about 3000 . . . 6000. Since noise influence increases frequency variations, the PLL circuit would require a large capacitor (e.g., 10 nF) external to the chip and connected by an unwanted extra pin. Integrating the capacitor would be difficult too; for example, the silicon area of such a capacitor would be larger than the area of the PLL circuit itself.
There in an ongoing need to provide an improved PLL circuit as well as a method that mitigate some or all of these and other disadvantages and limitations of the prior art.


REFERENCES:
patent: 5150386 (1992-09-01), Stern et al.
patent: 5774006 (1998-06-01), Barel et al.
patent: 5832048 (1998-11-01), Woodman, Jr.
Ronald E. Crochiere, Lawrence R. Rabiner; “Interpolation and Decimation of Digital Signals—A Tutorial Review”; Proceedings of the IEEE, vol.69, No. 3, Mar. 1981; pp. 417-447.

Affiliated with

Also associated with

Rating

Signal generator, and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Signal generator, and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signal generator, and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2929448