Signal generating circuit including delay-locked loop and...

Details Signal generating circuit including delay-locked loop and... Signal generating circuit including delay-locked loop and...

2004-05-26

2009-02-03

Ye, Lin (Department: 2622)

Television

Camera, system and detail

Solid-state image sensor

C348S312000, C348S374000, C327S149000, C327S158000, C327S161000

Reexamination Certificate

active

07486319

ABSTRACT:
According to a signal generating circuit including a delay-locked loop, a driving device including the signal generating circuit, and an image capturing apparatus including the signal generating circuit, when a rising edge designation signal for designating a predetermined rise time and a falling edge designation signal for designating a predetermined fall time are input, the signal generating circuit selects, from among a plurality of delay signals, a first delay signal rising at the time designated by the rising edge designation signal and a second delay signal rising at the time designated by the falling edge designation signal and outputs an output signal rising at the predetermined rise time and falling at the predetermined fall time by performing arithmetic processing on the first delay signal and the second delay signal.

REFERENCES:
patent: 6819729 (2004-11-01), Takagi
patent: 6909311 (2005-06-01), Foley et al.
patent: 2002/0075047 (2002-06-01), Tsukikawa
patent: 2002/0191094 (2002-12-01), Curtis et al.
patent: 2005/0093597 (2005-05-01), Kwak
patent: 11-341368 (1999-12-01), None
patent: 2000-341100 (2000-12-01), None
patent: 2002-016492 (2002-01-01), None
Japanese Office Action, Application No. 2003-168942.

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