Pulse or digital communications – Multilevel
Reexamination Certificate
1998-05-12
2001-10-09
Pham, Chi (Department: 2631)
Pulse or digital communications
Multilevel
Reexamination Certificate
active
06301309
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to circuits for selectively gating data signals, and in particular, to signal gating controllers for selectively gating out undesired pulses from improperly equalized data signals.
2. Description of the Related Art
Recovering data from data signals which have been transmitted over long lengths of cable at high data rates requires that such data signals be equalized in order to compensate for the signal loss and phase dispersion characteristics of the cable. Further, in those applications where the cable length may vary, such equalization must be capable of adapting according to the length of the cable. Conventional adaptive equalization is typically accomplished through the use of a feedback control signal having an amplitude which is proportional to the pulse height of the equalized data signal. However, such a technique for controlling the adaptive equalization process is very sensitive to amplitude errors in the incoming data signal and can often result in under-equalized or over-equalized signals. In such improperly equalized signals, false signal peaks can occur which result in false, and therefore undesired, decoded data pulses. Accordingly, it would be desirable to have a signal gating controller capable of gating out such false decoded data pulses and thereby compensate for improperly equalized signals.
SUMMARY OF THE INVENTION
A signal gating controller in accordance with the present invention monitors an equalized data signal and provides gating control signals for gating out false signal pulses caused by improper equalization of the original incoming data signal. Such a gating controller is particularly advantageous for use with a circuit for detecting and identifying valid detected errors in the signal peaks within such input data signal, such as that disclosed in co-pending, commonly assigned U.S. Pat. application Ser. No. 09/076,186, filed May 12, 1998, and entitled “Peak Error Detector” (attorney docket no. NSC1-A9010), the disclosure of which is incorporated herein by reference.
In accordance with one embodiment of the present invention, a signal gating control circuit includes a data signal level detection circuit and a gating control signal circuit. The data signal level detection circuit is configured to receive and detect an input data signal which includes a plurality of signal levels representing an N-level data signal and in accordance therewith provide first and second data peak signals. The input data signal includes, associated therewith: sequential intermediate signal levels, sequential positive peak signal levels each of which is positive with respect to a preceding one of the sequential intermediate signal levels, and sequential negative peak signal levels each of which is negative with respect to a preceding one of the sequential intermediate signal levels. The first data peak signal includes primary and secondary first data peak signal pulses which are asserted when the input data signal level has transitioned beyond a first predetermined value. The second data peak signal includes primary and secondary second data peak signal pulses which are asserted when the input data signal level has transitioned beyond a second predetermined value. The secondary first and second data peak signal pulses are asserted immediately subsequent to de-assertion of the primary second and first data peak signal pulses, respectively. The first predetermined value corresponds to a first value which is between a preceding one of the plurality of sequential intermediate signal levels and a first preceding one of the pluralities of sequential positive and negative peak signal levels. The second predetermined value corresponds to a second value which is between a preceding one of the plurality of sequential intermediate signal levels and a second preceding one, which is opposite to the first preceding one, of the pluralities of sequential positive and negative peak signal levels. The gating control signal circuit is coupled to the data signal level detection circuit and is configured to receive and process the first and second data peak signals and in accordance therewith provide first and second gating control signals, respectively. Logical combinations of the first and second gating control signals and the second and first data peak signals provide third and fourth data peak signals in which the primary second and first data peak signal pulses remain and the secondary second and first data peak signal pulses are removed, respectively.
These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings.
REFERENCES:
patent: 5844439 (1998-12-01), Zortea
patent: 5880615 (1999-03-01), Bazes
Kurt H. Mueller and Markus Müller, “Timing Recovery in Digital Synchronous Data Receiver”, IEEE Transactions on Communications, vol. COM-24, No. 5, May 1976, pp. 516-531.
Hee Wong
Phanse Abhijit
Baker & McKenzie
Corrielus Jean B
National Semiconductor Corporation
Pham Chi
LandOfFree
Signal gating controller for enhancing convergency of MLT3... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Signal gating controller for enhancing convergency of MLT3..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signal gating controller for enhancing convergency of MLT3... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2600382