Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1988-06-29
1989-04-18
Miller, Stanley D.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307246, 307482, 307270, 307578, 307597, 307451, H03K 500, H03K 1756, H03K 301, H03K 17687
Patent
active
048230243
ABSTRACT:
A MOS circuit for trimming a digital pulse signal by delaying the rising edge of the pulse signal for a predetermined period of time and passing the falling edge without delay. The circuit includes two MOS output transistors and a signal buffer. The signal buffer has a number of stages for delaying the pulse signal, with the number chosen to control the delay in the rising edge of the pulse signal. One of the output transistors receives the pulse signal at its drain and is enabled by the delayed pulse signal from the signal buffer to pass the pulse signal after the predetermined period of time to its source at the output of the circuit, so that the rising edge is delayed, but the falling edge is not. The other output transistor is enabled to ground the output of the circuit after the falling edge of the pulse signal. A self-booting circuit drives the gate of the one output transistor to assure that the voltage level of the trimmed signal will not be reduced by dissipation across the transistor.
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M. Annaratone, "Digital CMOS Circuit Design", 90 (1986).
Donahue James A.
Sanwo Ikuo J.
Tipon Donald G.
Hawk Jr. Wilbert
Jewett Stephen F.
Miller Stanley D.
NCR Corporation
Phan Trong Quang
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