Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Diverging with single input and plural outputs
Reexamination Certificate
1999-09-23
2001-11-27
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Diverging with single input and plural outputs
C327S099000
Reexamination Certificate
active
06323716
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a signal distributing circuit and a signal line connecting method, and more particularly, to a signal distributing circuit and a signal line connecting method which prevent or reduce skew, the time difference when a signal to be distributed is input into each of a plurality of loads.
A signal distributing circuit is configured to distribute a signal to many loads (circuits). Loads (circuits) are, for example, internal circuits (flip-flops and the like) in a data processing device which can be large such as a supercomputer, or small such as a microprocessor (integrated circuit), and the like. In a synchronous data processing device which is configured such that many internal circuits (flip-flops and the like) operate synchronously with one another, a signal distributing circuit is typically used for distributing a clock signal which is used as a basis for providing the timing for synchronizing the respective internal circuits with one another.
In such a signal distributing circuit, skew is caused by the difference in signal propagation time due to ununiformity of signal distributing paths to the respective loads. Therefore it is necessary to reduce skew to attain a high performance device.
Skew creates a timing problem in a synchronous data processing device because a clock distributing circuit may provide skew of a clock signal to different parts inside the device. In order to prevent this problem, the device must be operated by a clock cycle time that can guarantee that each data signal can reach destination internal circuits (flip-flop for example) before a clock reaches them, even assuming a large amount of skew. The greater the skew, the longer the clock cycle time must become. If the clock cycle time becomes longer, however, the operation speed of the device is reduced.
One cause of skew in a signal distributing circuit is the difference in signal propagation time generated among the respective portions in the circuit due to variations in the manufacturing process. In a clock distributing circuit whose circuit scale extends over the entire device, a serious problem is created because a particularly large skew is generated.
This problem can be solved by manufacturing more uniform circuits by improving the manufacturing process of the circuits, and as a result, creating less variation among the respective portions in the circuits. However, because the cost of manufacturing these uniform circuits is higher than the normal manufacturing process, this method is economically impractical.
The other cause of skew is the difference in signal propagation time caused by the ununiformity of signal distributing paths each connecting between portions of the circuit. When a clock distributing circuit is provided in a large-scale synchronous data processing device, another serious problem is created because there are a number of clock distributing paths over the entire device.
FIG. 5
shows a first conventional signal distributing circuit which address the above problems as disclosed in Japanese Patent Application Laid-open Hei No.4-205,326. The circuit includes a tree-type hierarchy in which a layer-to-layer connection from the upper to the lower layer is a one-to-one connection.
In
FIG. 5
, a main oscillator
10
supplies a synchronizing clock signal to each of processors
130
in a manner of a tree structure through m distributors
110
, each of which distributes the clock signal to m parts, and n distributors, each of which distributes it to n parts.
In the first conventional circuit, because each connection between layers from the upper to the lower layer is a one-to-one connection and each layer requires the distributor, the number of distributors increase proportionally as the number of loads (processors) increase, thus the scale of the entire circuit becomes factorially large. As the result, skew, which is caused by variation in the characteristic of the distributing paths, increases proportionally as the number of loads (processors) increase. In addition, because the number of layers of the entire circuit need to be changed when the number of loads (processors) change greatly, it is not easy to change the number of loads (processors). While the scale of the entire circuit can be kept small by making each layer-to-layer connection from the upper to the lower layer into a one-to-n (plural loads) connection, skew becomes larger due to a propagation delay time difference between signals influenced by the order of connection of the respective loads in each layer-to-layer connection or due to noise caused by multiple reflections of a propagated signal wave between the respective loads.
U.S. Pat. No.4,447,870 discloses a technique for manually adjusting (or controlling by an operator) a signal (clock) distributing circuit (hereinafter, refered to a second conventional circuit).
In the second conventional circuit, a problem occurs because a manual or operator control adjustment is required and, particularly, in a large-scale device, it is necessary to manage delay quantities by adjusting each of the many circuits in each signal distributor layer. This increases man power or equipment. In addition, there is another problem that skew, which is caused by a factor which occurs later such as a temperature change, cannot be compensated by an initial skew adjustment.
Japanese Patent Application Laid-open publication Hei No. 4-205,326 also discloses a signal distribution circuit of a third conventional circuit.
In
FIG. 6A
, the circuit includes a main oscillator
10
, and two transmission lines, a forward transmission line A, and a backward transmission line B, which are opposite to each other in transmission direction and are connected to main oscillator
10
. Transmission line A is bent at point a and transmission line B is bent at point b so that they are symmetrical to each other with respect to main oscillator
10
, and they are arranged to be adjacent to each other, opposite in transmission direction and parallel with each other within a specified length L
0
. Processors
20
,
30
, . . . , and N are connected to transmission lines A and B. Although connecting points of each processors and transmission lines A and B are shown at positions slightly apart from each other as shown in
FIG. 6A
, the points are at the same positions on transmission lines A and B.
As represented by a processor
20
, each of the processors includes a phase difference detecting element
200
and a clock oscillating element
300
. Clock signals from transmission lines A and B are input to phase difference detecting element
200
. Phase difference detecting element
200
detects a phase difference between the clock signals. Clock oscillating element
300
generates a clock signal for controlling a processor based on the phase difference between the clock signals detected by phase difference detecting element
200
.
Next, the operation of the third conventional circuit will be described.
The two transmission lines A and B are supplied with clock signals from main oscillator
10
. Transmission line A has a clock signal input from the processor N side and transmission line B has a clock signal input from the processor
20
side. Since transmission lines A and B have a uniform characteristic, the delay amount of transmission line A increases linearly as shown by a straight line A in
FIG. 6B
from a reference point a, while the delay amount of transmission line B increases linearly as shown by a straight line B in
FIG. 6B
from a reference point b.
Processor
20
inputs clock signals from point a
n
of transmission line A and point b
1
of transmission line B. Because the delay amount of the clock at point a
n
is as shown in
FIG. 6B
as point a
n
on the straight line A and the delay amount of the clock at point b
1
on transmission line B is as shown in
FIG. 6B
as point b
1
on the straight line B, their middle point n can be obtained by adding the delay amounts of points a
n
and b
1
and halving the added result.
Clock signals transmitted by transm
NEC Corporation
Nu Ton My-Trang
Sughrue Mion Zinn Macpeak & Seas, PLLC
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