Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2002-03-06
2003-06-17
Tokar, Michael (Department: 2819)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C340S815440, C345S100000, C345S099000, C345S098000
Reexamination Certificate
active
06580412
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The invention relates to a signal display apparatus and an associated method, and more particularly, to a signal display apparatus and a method for storing a sequential data flow into shift registers of the signal display apparatus non-consecutively.
2. Description of the Prior Art
In modern information society, data is typically digitized into binary files for facilitating the processing of a huge amount of information via a semiconductor circuit. Each bit of data in the binary file is arranged in sequence to constitute a data flow so as to form the most fundamental digital data. Since the constituent bits of the digital data is arranged in a time sequence, a digital circuit is merely required to process a few bits of the sequential digital data at the same time. Thus, the design of the digital circuit can be substantially simplified and the layout dimensions of the digital circuit can be considerably reduced.
Among various types of digital circuits, a data register circuit for storing sequential data in a series manner is a fundamental constituent block. Please refer to FIG.
1
.
FIG. 1
is a function block diagram illustrating a combination of a conventional data register circuit
12
and a conventional interface circuit
10
. The conventional interface circuit
10
has two output ends for outputting a sequential data signal
16
and a corresponding first clock
14
, respectively. The data register circuit
12
is used to cooperate with the first clock
14
for storing the data signal
16
outputted from the interface circuit
10
. The data register circuit
12
comprises two shift registers
18
A and
18
B with the same function, and which are referred to as the first shift register
18
A and the second shift register
18
B. Both of the shift registers
18
A and
18
B comprise a plurality of register units
19
which electrically connect to each other in a series manner. As shown in
FIG. 1
, four register units
19
are installed in the respective shift registers
18
A,
18
B for illustration. Each of the register units
19
is used to store a bit of data. The register unit
19
located on the right most side of the first shift register
18
A is electrically connected to the register unit
19
located on the left most side of the second shift register
18
B. Additionally, the first and second shift registers
18
A and
18
B have respective clock ends
22
for receiving triggers of the first clock
14
outputted from the interface circuit
10
to control operations of the first and second shift registers
18
A and
18
B.
The data register circuit
12
further comprises a display circuit
20
for displaying the sequential data stored in the data register unit
12
. Explicitly speaking, the display circuit
20
has a plurality of display units
24
, each of the display units
24
electrically connected to the corresponding register unit
19
for displaying the data in the corresponding register unit
19
. The typical example of the display unit
19
is a light emitting diode (LED). The LED can be bright or dark depending on the conduction condition of the LED so as to represent the data of “1” or “0” stored in the corresponding register unit
19
, respectively. The display circuit
20
has a variety of applications such as a network switch.
Since a plurality of terminals on the network exchange information with each other via the network switch, a display interface is required to display operational statuses of each of the terminals. A network administrator can thus conveniently monitor the operational statuses of each of the terminals on the network. For example, the network switch can utilize the circuit configuration shown in
FIG. 1
to be the display interface. Under this situation, the four register units
19
of the first shift register
18
A can be used to store four different types of the operational statuses for a first terminal. The operational statuses of a terminal could be the on-line status, the status of data transferring, the status of data collision, and so forth. Likewise, the second shift register
18
B can be used to store four different types of the operational statuses for a second terminal. Data that represents the operational statuses for the respective terminals are provided to the data register circuit
12
in a series manner from the interface circuit
10
with reference to the first clock
14
. Therefore, the display circuit
20
that cooperates with the first and second shift registers
18
A and
18
B can be used to display the related operational statuses of the first and second terminals via the display units
24
. When the display units
24
are LEDs, the way for displaying the operational statuses of the terminals is to emit or to dim the light of the LEDs.
Please refer to FIG.
2
.
FIG. 2
is a timing diagram illustrating the relationship between the conventional first clock
14
with the conventional sequential data signal
16
, both being outputted from the interface circuit
10
. The horizontal axis of
FIG. 2
represents time. With reference to the eight register units
19
in the data register circuit
12
, one set of data
26
in the sequential data signal
16
has eight bits
16
A,
16
B,
16
C,
16
D,
16
E,
16
F,
16
G,
16
H. Among the data
26
, the bits
16
A to
16
D are high-order (most significant) bits
26
B, and the bits
16
E to
16
H are low-order (least significant) bits
26
A. Furthermore, corresponding to each of the bits in the data
26
, the first clock
14
also has eight corresponding clock periods
14
A,
14
B,
14
C,
14
D,
14
E,
14
F,
14
G,
14
H. Each of the clock periods has a period of T and is used to trigger operations of the first and second shift register
18
A and
18
B.
Please refer to
FIGS. 3A
to
3
D.
FIGS. 3A
to
3
D are schematic diagrams illustrating the operations of the conventional data register circuit
12
with the trigger of the first clock
14
at different clock periods. For clarity of description, the situation of storing the data
26
of
FIG. 2
into the data register circuit
12
is taken as an example. The first register unit in the first shift register
18
A is designated as the register unit
19
A, and the second register unit in the first shift register
18
A is designated as the register unit
19
B. According to this designation, the register unit positioned at the right most side of the second shift register
18
B is designated as the register unit
19
H. The eight bits
16
A to
16
H of the data
26
have respective content of 1, 0, 1, 0, 0, 1, 1, 0, corresponding to the clock periods
14
A to
14
H of the first clock
14
, respectively.
As shown in
FIG. 3A
, when the clock period
14
A of the first clock
14
triggers the data register circuit
12
, both of the first and second shift register
18
A and
18
B shift each of the bits in the respective register units
19
one bit right. Thus, the register unit
19
A in the first shift register
18
A is filled in with the first bit
16
A of the data
26
, and the numeral
23
is used to represent the content of the bit
16
A. As shown in
FIGS. 3A
to
3
D, arrows
28
are used to represent the movements toward the right-hand side for each of the bits in the data register circuit
12
, and a symbol X is used to represent data stored in each of the register units
19
before the data
26
is shifted into the data register circuit
12
. As shown in
FIGS. 2 and 3A
, the bit
16
A is the first transferred bit in the data signal
16
.
As time goes by, each of the clock periods of the first clock
14
triggers the first and second shift registers
18
A and
18
B to shift the content in each of the register units
19
to the respective adjacent right register unit
19
so as to store the bits of the data
26
successively. As shown in
FIG. 3B
, at the clock period
14
B, the two bits
16
A and
16
B of the data
26
have been stored in the data register circuit
12
. The bit
16
A, which was originally stored in the register unit
19
A of the first shift register
18
A, is shif
Duh Ming-Yih
Lin Yen-Shan
Sung Da-Cheng
Tan Vibol
Tokar Michael
VIA Technologies Inc.
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