Signal detector including sample and hold circuit with reduced o

Details Signal detector including sample and hold circuit with reduced o Signal detector including sample and hold circuit with reduced o

1978-08-23

1980-10-21

Martin, John C.

Facsimile and static presentation processing

Static presentation processing

Attribute control

331 20, 331 25, H04N 946, H03B 304

Patent

active

042297591

ABSTRACT:
A sample and hold detector arrangement suitable for construction in integrated circuit form as an automatic chroma gain control detector, or a color oscillator AFPC detector, or the like. A wide bandwidth analog multiplier circuit is supplied with an intermittent reference signal and a second signal, the phase or amplitude of which is to be sampled. In a preferred embodiment, the reference signal corresponds to the burst component of a composite color television signal and the second signal corresponds to a locally generated color subcarrier signal. The multiplier provides oppositely phased output signals which are coupled to first and second sample and hold circuits. Each sample and hold circuit is keyed to concurrently sample the respective multiplier outputs for the same sampling interval, and each provides substantially symmetrical bidirectional conduction to associated filter capacitors during the sampling interval and a high holding impedance during the remainder of each cycle.

REFERENCES:
patent: 3585285 (1971-06-01), Rennick
patent: 3740456 (1973-06-01), Harwood
patent: 3860954 (1975-01-01), Tsuchiya
patent: 4056826 (1977-11-01), Watanabe et al.

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