Signal delaying outputting circuit

Details Signal delaying outputting circuit Signal delaying outputting circuit

1994-12-14

1996-06-04

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327288, 327513, 327276, H03K 1714, H03K 513

Patent

active

055237118

ABSTRACT:
A signal delaying outputting circuit is disclosed which can prevent an excessive increase in dead time at a high temperature without requiring a large chip area. The signal delaying outputting circuit comprises a first invertor circuit driven by an input signal, and a second invertor circuit driven by an output signal of the first invertor circuit. A first auxiliary MOS FET of the same channel type as that of one of two first p- and n-channel MOS FETs of the first invertor circuit is provided in the first converter circuit in an integral continuous relationship with the one MOS FET such that they have separate gates from each other but have a common source or drain. A second auxiliary MOS FET of the same channel type as that of one of second p- and n-channel MOS FETs of the second invertor circuit but different from that of the first auxiliary MOS FET is provided in the second invertor circuit in an integral continuous relationship such that they have separate gates from each other but have a common source or drain. The first and second auxiliary MOS FETs are switched in response to a binary output signal of a temperature detection circuit.

REFERENCES:
patent: 4473762 (1984-09-01), Iwahashi et al.
patent: 4988897 (1991-01-01), Jeong
patent: 5118971 (1992-06-01), Schenck
patent: 5121014 (1992-06-01), Huang
patent: 5231319 (1993-07-01), Crafts et al.
patent: 5291071 (1994-03-01), Allen et al.

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