Signal delay skew reduction system

Details Signal delay skew reduction system Signal delay skew reduction system

2011-08-09

2011-08-09

Doan, Nghia M (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S106000, C716S107000, C716S108000, C716S110000, C716S111000, C716S112000, C716S113000, C716S132000, C716S134000, C703S013000, C703S014000

Reexamination Certificate

active

07996804

ABSTRACT:
A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.

REFERENCES:
patent: 6550044 (2003-04-01), Pavisic et al.
patent: 6782520 (2004-08-01), Igusa et al.
patent: 7047504 (2006-05-01), Kawano
patent: 7694242 (2010-04-01), Li et al.

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