Signal delay computing method

Details Signal delay computing method Signal delay computing method

1996-12-19

1998-10-06

Barlow, Jr., John E.

Data processing: measuring, calibrating, or testing

Measurement system in a specific environment

Electrical signal parameter measurement system

364488, 364489, 364490, 327270, 327278, G06F 1500

Patent

active

058192050

ABSTRACT:
It is an object to provide a signal delay computing method for efficiently improving the accuracy of signal delay values. First, a space (SPi) including a load capacitance value (C1), a load resistance value (R1) and a transition delay value (D0) is selected. Next, eight vertexes (u1 to u8) of the space (SPi) are extracted. The vertex uk (k=1 to 8) is represented by coordinates as (C1.sub.uk, R1.sub.uk, D0.sub.uk, D1.sub.uk). The combination of these values about one vertex are known by circuit simulation. Next, substitution of the values of the coordinates into a delay computing equation is performed in order for all of the integers k=1 to 8. Then eight simultaneous equations are obtained. The simultaneous equations are solved to determine the values of the coefficients (W.sub.0i to W.sub.7i) in the delay computing equation. The coefficients (W.sub.0i to W.sub.7i) determined, the load capacitance value (C1), the load resistance value (R1) and the transition delay value (D0) are substituted into the delay computing equation to determine an objective transition delay value (D1).

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