Signal delay apparatus employing a phase locked loop

Details Signal delay apparatus employing a phase locked loop Signal delay apparatus employing a phase locked loop

1991-10-24

1992-09-08

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307608, 307262, 307 55, 307155, H03K 513, H03K 5159

Patent

active

051461218

ABSTRACT:
An apparatus is provided for delaying digital data signals by fixed amounts within an integrated circuit. A delay lock loop includes an adaptive delay line, a phase detector and an integrator. The integrator provides control signals c.sub.p, c.sub.n for controlling the delay line, in dependence upon the relative phase of a reference clock signal .phi..sub.0 and a delayed clock signal .phi..sub.n. The delay line includes a plurality of delay cells. By maintaining a phase relationship .phi..sub.n =.phi..sub.0 +360.degree. one clock cycle, T.sub.c, delay through the delay line is provided. Thus each delay cell provides T.sub.c
delay. By placing identical cells in signal paths elsewhere on a chip, fixed delays can be introduced which are controlled by the delay lock loop.

REFERENCES:
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patent: 4641048 (1987-02-01), Pollock
patent: 4795923 (1989-01-01), Dobos
patent: 4922141 (1990-05-01), Lofgren et al.
patent: 4994687 (1991-02-01), Fujii et al.
patent: 5059838 (1991-10-01), Motegi et al.
patent: 5066877 (1991-11-01), Hamano et al.

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