Signal computing bus

Details Signal computing bus Signal computing bus

1993-03-01

1995-04-25

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 8511, 3701001, 34082506, H04J 312, H04Q 1104

Patent

active

054105420

ABSTRACT:
A signal computing bus (SCbus) includes two bus structures: (a) a synchronous TDM data transport referred to as a data bus and (b) a serial message passing bus referred to as a message bus. The following three groups of functions are performed using the SCbus: (a) data transport over the data bus, (b) message passing over the message bus, and (c) data and message bus control. In a preferred embodiment, the data bus utilizes: 2 clocks, 1 frame pulse, 16 data busses, and 1 clock control (the clock control signal enables access to the bus and automatic switching from one clock master to another when an error is detected) and the message bus is fabricated using a master HDLC protocol with contention resolution.

REFERENCES:
patent: 4656627 (1987-04-01), Hasley et al.
patent: 4835773 (1989-05-01), Kuwahara et al.
patent: 5107492 (1992-04-01), Roux et al.
patent: 5202883 (1993-04-01), Hatherill et al.
patent: 5291479 (1994-03-01), Vaziri et al.

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