Signal buffer circuit arrangement

Details Signal buffer circuit arrangement Signal buffer circuit arrangement

1978-09-21

1981-08-04

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307243, 307259, 307262, 307DIG1, 328118, H03K 1766, H03K 1776, H03K 5156

Patent

active

042824478

ABSTRACT:
An interface device for selectively accessing two internal signal paths of an integrated circuit through a single external connection pin. Each of the signal paths is provided with a bias voltage sensitive conduction device that permits conduction at a different externally provided bias voltage that inhibits current flow in the other conduction device. The different bias voltages are provided to the external connection pin through an external load resistor.

REFERENCES:
patent: 2728866 (1955-12-01), Edwards
patent: 2864961 (1958-12-01), Lohman et al.
patent: 3032679 (1962-05-01), Roberts, Jr. et al.
patent: 3077545 (1963-02-01), Rywak
patent: 3103597 (1963-09-01), Novick et al.
patent: 3146357 (1964-08-01), Spallone
patent: 3311751 (1967-03-01), Maestre
patent: 3471714 (1969-10-01), Gugliotti, Jr. et al.
patent: 3479531 (1969-11-01), Gauld
patent: 3790823 (1974-02-01), Briley
patent: 4010385 (1977-03-01), Krol

Affiliated with

Also associated with

Rating

Signal buffer circuit arrangement does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Signal buffer circuit arrangement, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signal buffer circuit arrangement will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-242211