Signal amplifier circuit and optical receiver

Amplifiers – Sum and difference amplifiers

Reexamination Certificate

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Details

C330S110000, C330S308000, C250S2140AG, C250S2140AG, C327S309000

Reexamination Certificate

active

07952427

ABSTRACT:
A signal amplifier circuit includes peak value holding circuit11receiving positive-phase input signal, peak value holding circuit12receiving negative-phase input signal, adder13adding the positive-phase input signal and output signal of peak value holding circuit12, adder14adding the negative-phase input signal and output signal of the peak value holding circuit11, non-inverting amplifier15amplifying output signal of adder13, non-inverting amplifier16amplifying output signal of adder14, peak value holding circuit21receiving positive-phase output signal of non-inverting amplifier15, peak value holding circuit22receiving negative-phase output signal of non-inverting amplifier16, adder23adding the positive-phase output signal and output signal of peak value holding circuit22, adder24adding the negative-phase output signal and output signal of peak value holding circuit21, and differential amplifier29amplifying difference between output signals of adders23and24. Error in discrimination for small-amplitude signal embedded in tail is reduced.

REFERENCES:
patent: 5612810 (1997-03-01), Inami et al.
patent: 5892609 (1999-04-01), Saruwatari
patent: 6115163 (2000-09-01), Nobuhara
patent: 6587004 (2003-07-01), Ide
patent: 6819722 (2004-11-01), Hatakeyama
patent: 6965257 (2005-11-01), Tanaka
patent: 8084160 (1996-03-01), None
patent: 2656734 (1997-05-01), None
patent: 10084231 (1998-03-01), None
patent: 11-112439 (1999-04-01), None
patent: 2004072710 (2004-03-01), None
patent: 3606143 (2004-10-01), None
patent: WO 01/48914 (2001-07-01), None

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