Signal adjustment for duty cycle control

Details Signal adjustment for duty cycle control Signal adjustment for duty cycle control

2005-02-18

2009-02-10

Tra, Quan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S035000, C327S038000, C327S176000

Reexamination Certificate

active

07489173

ABSTRACT:
Signal phase adjustment for duty cycle control is described. A first sample clock signal and a second sample clock signal are provided. A first phase signal and a second phase signal are generated responsive to the first sample clock signal, where the first phase signal is out of phase with respect to the second phase signal. The second sample clock signal configured to be swept in phase in relation to the first phase signal. A combined signal is generated where the combined signal has a duty cycle associated with the first phase signal and the second phase signal in combination. A first counter and a second counter are clocked responsive to the second sample clock signal to count. A first count from the first counter is divided by a second count from the second counter to obtain the duty cycle associated with the combined signal.

REFERENCES:
patent: 4239992 (1980-12-01), Perkins
patent: 4338569 (1982-07-01), Petrich
patent: 5097208 (1992-03-01), Chiang
patent: 5256916 (1993-10-01), Thurston
patent: 5367200 (1994-11-01), Leonida
patent: 5455530 (1995-10-01), Huppenthal et al.
patent: 5714896 (1998-02-01), Nakagawa et al.
patent: 5790479 (1998-08-01), Conn
patent: 5877632 (1999-03-01), Goetting et al.
patent: 5914616 (1999-06-01), Young et al.
patent: 5923621 (1999-07-01), Kanekal et al.
patent: 6005829 (1999-12-01), Conn
patent: 6069849 (2000-05-01), Kingsley et al.
patent: 6144262 (2000-11-01), Kingsley
patent: 6212126 (2001-04-01), Sakamoto
patent: 6219305 (2001-04-01), Patrie et al.
patent: 6232845 (2001-05-01), Kingsley et al.
patent: 6233205 (2001-05-01), Wells et al.
patent: 6263034 (2001-07-01), Kanack et al.
patent: 6324485 (2001-11-01), Ellis
patent: 6356514 (2002-03-01), Wells et al.
patent: 6404840 (2002-06-01), Sindalovsky
patent: 6424190 (2002-07-01), Kim
patent: 6445245 (2002-09-01), Schultz et al.
patent: 6452489 (2002-09-01), Ehrlich
patent: 6501313 (2002-12-01), Boerstler et al.
patent: 6509771 (2003-01-01), Atallah et al.
patent: 6549571 (2003-04-01), Baba
patent: 6642760 (2003-11-01), Alon et al.
patent: 6687865 (2004-02-01), Dervisoglu et al.
patent: 6777980 (2004-08-01), Young et al.
patent: 7062692 (2006-06-01), Lesea
U.S. Appl. No. 10/683,944, Young, filed Oct. 10, 2003.
Xilinx, Inc., “The Programmable Logic Data Book,” 2000, pp. 3-75 to 3-96, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA. 95124.
Xilinx, Inc., “Virtex-II Pro Platform FPGA Handbook”, Dec. 2000, pp. 33-75, DS031, v 1.1, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA. 95124.
Xilinx, Inc., “Virtex-II Pro Platform FPGA Handbook”, Oct. 2002, DS083-1, pp. 19-71, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA. 95124.
U.S. Appl. No. 10/402,837, filed Mar. 27, 2003, Lesea, A. et al., Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.

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