Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2006-12-22
2008-12-02
Nguyen, Khai M (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S077000
Reexamination Certificate
active
07460046
ABSTRACT:
Sigma-delta modulators and a method of modulating are disclosed in which a first sigma-delta modulator having a first quantizer is provided, and a second quantizer is also provided. At least a first node of the first sigma-delta modulator upstream of the first quantizer and a second node of the first sigma-delta modulator upstream of the first quantizer to the second quantizer are coupled together.
REFERENCES:
patent: 4862169 (1989-08-01), van Bavel et al.
patent: 5068661 (1991-11-01), Kaneaki et al.
patent: 5103229 (1992-04-01), Ribner
patent: 5124703 (1992-06-01), Kaneaki et al.
patent: 5153593 (1992-10-01), Walden et al.
patent: 5274374 (1993-12-01), Powell et al.
patent: 5416483 (1995-05-01), Matsuya
patent: 5500645 (1996-03-01), Ribner et al.
patent: 6300890 (2001-10-01), Okuda et al.
patent: 6323794 (2001-11-01), Okuda et al.
patent: 6496128 (2002-12-01), Wiesbauer et al.
patent: 6518904 (2003-02-01), Jelonnek
patent: 6538589 (2003-03-01), Okuda et al.
patent: 6873281 (2005-03-01), Esterberg et al.
patent: 7084797 (2006-08-01), Yokoyama et al.
A. Maloberti, “High-seepd data converters for communication systems,” IEEE Circuits Syst. Mag., vol. 1, pp. 26-36, First Quarter 2001.
P. Malcovati, et al., “Behavioral modeling of switched-capacitor sigma-delta modulators”, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, pp. 352-364, Mar. 2003.
J: Riuz-Amaya et al., “High-level synthesis of switched-capacitor, switched-current . . . ,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, pp. 1795-1810, Sep. 2005.
F. Colodro, et al., “Time interleaved multirate sigma-delta modulators,” in Proc. IEEE ISCAS, 2005, pp. 5581-5584.
G: Bernardinis, et al., “A wide-band 280-MHz four-path time-interleaved bandpass sigma-delta . . . ”, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, pp. 1423-1432, Jul. 2006.
T.C. Caldwell, et al., “A time-interleaved continuous-time sigma-delta modulator with 20 MHz signal bandwidth,” IEEE J. Solid-State Circuits, vol. 41, pp. 1578-1588, Jul. 2006.
F. Colodro, et al., “Multirate sigma-delta modulators,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, pp. 170-176, Mar. 2002.
F. Colodro, et al., “New multirate bandpass sigma-delta modulators,” IEEE Trans. Circuits Syst. I, Reg. Papres, vol. 51, pp. 2141-2147, Nov. 2004.
M. Yavari, et al., “Double-sampling single-loop sigma-delta modulator topologies for . . . ,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, pp. 314-318, Apr. 2006.
P. Rombouts, et al., “Systematic design of double-sampling sigma-delta A/D converters with . . . ,” IEEE TRans. Circuits Syst. II, Exp. Briefs, vol. 51, pp. 675-679, Dec. 2004.
J. Paramesh, et al., “An 11-bit 330MHz 8× OSR sigma-delta modulator for next-generation WLAN,” in Proc. IEEE VLSI, 2006.
L. A. Williams, et al., “Third-order cascaded sigma-delta modulators,” IEEE Trans. Circuits Syst., vol. 38, pp. 489-498, May 1991.
L.J. Breems, et al. “A cascaded continuous-time sigma-delta modulator with 67-dB dynamic range in 10MHz . . . ,” IEEE J. Solid-State Circuits, vol. 39, pp. 2152-2160, Dec. 2004.
S. Rabii, et al., “A 1.8-V digital-audio sigma-delta modulator in 0.8-m CMOS,” IEEE J. solid-State Circuits, vol. 32, pp. 783-796, Jun. 1997.
F. Medeiro, et. al., “A 13-bit, 2.2-MS/s, 55-mW multibit cascade sigma-delta modulator in CMOS 0.7-m single- . . . ” IEEE J. Solid-State Circuits, vol. 34, pp. 748-760, Jun. 1999.
R. Del Rio, et al., “Highly linear 2.5-V CMOS sigma-deltamodulator for ADSL+,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, pp. 47-62, Jan. 2004.
O. Oliaei, et al., “A 5mW sigma-delta modulator with 84-dB dynamic range for GSM/EDGE,” IEEE J. Solid-State Circuits, vol. 37, pp. 2-10, Jan. 2002.
A. Tabatabaei, et al., “A dual channel sigma-delta ADC with 40MHz aggregate signal bandwidth,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 66-67.
K. Vleugels, et al., “A 2.5-V sigma-delta modulator for boardband communications applications,” IEEE J. Solid-State Circuits, vol. 36, pp. 1887-1899, Dec. 2001.
M. Ostmanns, et al., “A case study on a 2-1-1 cascaded continuous-time sigma-delta modulator,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, pp. 1515-1525, Aug. 2005.
R. Tortosa, et al., “A new high-level synthesis methodology of cascaded continuous-time . . . , ” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, pp. 739-743, Aug. 2006.
R. Rutten, et al., “Digital calibration of a continuous-time cascaded sigma-delta modulator based on variance derivative estimation,” in Proc. IEEE ESSCIRC, 2006.
Z. Zheng, et al., “Sigma-delta modulators with interstage gain scaling,” in Proc. IEEE MWSCAS, 2000, pp. 40-43.
L. Fang, et al., “A multi-bit sigma-delta modulator with interstage feedback,” in Proc. IEEE ISCAS, 1998, pp. 583-586.
C.H. Su, et al., “A fourth-order cascaded sigma-delta modulator with DAC error cancellation technique,” in Proc. IEEE MWSCAS, 2002. pp. 132-135.
Chon-In Lao, et al., “A novel semi-MASH sub-stage for high-order cascade sigma-delta modulators,” in Proc. IEEE ISCAS, 2005, pp. 3095-3098.
R. Schreier, et al., “An empirical study of high-order single-bit delta-sigma modulators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, pp. 461-466, Aug. 1993.
J. Markus, et al., “An efficient sigma-delta ADC architecture for low . . . ,” IEEE Trans.Circuits Syst. II, Analog Digit. Signal Process., vol. 40, pp. 63-71, Jan. 2004.
G.J.Gomez, “A 102-dB spurious-free DR sigma-delta ADC using a dynamic dither . . . ,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, pp. 531-535, Jun. 2000.
F.Medeiro, et al., “Fourth-order cascade SC sigma-delta modulators: a comparative . . . ,” IEEE Trans. Circuits Syst. I, Funndam. Theory Appl., vol. 45, pp. 1041-1051, Oct. 1998.
A. Marques, et al., “Optimal parameters for sigma-delta modulator topologies,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, pp. 1232-1241, Sep. 1998.
A.Gharbiya, et. al., “On the implementation of input-feedforward delta-sigma modulators,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, pp. 453-457, Jun. 2006.
J.A. Cherry, et. al., “Excess loop delay in continuous-time delta-sigma . . . ,” IEEE Trans. Circuits Syst. II, Analog Digit. SIgnal Process, vol. 46, pp. 376-389, Apr. 1998.
H. Aboushady, et al., “Systematic approach for discrete-time to continuous-time transformation of sigma-delta modulators,” in Proc. IEEE ISCAS, 2002, pp. 229-232.
S.Loeda, et al., “On the design of high-performance wide-band cintinuous-time sigma-delta . . . ,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, pp. 802-810, Apr. 2006.
Y. Yi, et al., “A cascade 3-1-1 multibit sigma-delta A/D modulator with reduced sensitivity to non-idealities,” in proc. IEEE ISCAS, 2005, pp. 3087-3090.
R. Schreier G. Temes. “Understanding Delta-Sigma Data-Converters,” Wiley Interscience, 2005, pp. 122-137.
J. De Maeyer, et al., “Controlled behaviour of STF in CT sigma-delta modulators,” Electronics Letters, vol. 41 No. 16, Aug. 2005.
Di Giandomenico Antonio
Hernandez Luis
Paton Susana
San Segundo Bello David
Sanchez-Renedo Manuel
Infineon - Technologies AG
Nguyen Khai M
Patent Department Infineon Technologies
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