Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
1999-11-17
2001-08-14
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
Reexamination Certificate
active
06275177
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a sigma-delta modulator (SDM), particularly to a highly stabilized sigma-delta modulator using a LNFL (Local Nonlinear Feedback Loop) technique for resolving overload problems.
2. Description of the Related Art
A variety of sigma-delta modulators (SDMs), such as a so-called oversampled SDM, are used for fabricating analog-to-digital converters (ADC). The ADC comprising an oversampled SDM mainly employs oversampling and noise shaping techniques of the SDM for reducing quantization noise and shaping it to a higher frequency. Then the high frequency noise is filtered out with a decimator and a digital lowpass filter to enhance the signal-to-noise ratio (SNR) and to obtain high resolution. Further, the SDM has the following advantages: simple construction, no need for an additional trimming circuit, and high tolerance of variation in circuit components. Consequently, the SDM is used widely in situations where SNR needs to be enhanced.
The architecture of SDMs falls into two categories: classical and cascaded SDMs.
FIGS. 1A-1C
illustrate the architecture of a classical SDM. In the Figures, the order of the noise shaping factor of the SDM is determined by the number of the cascaded integrators in the SDM.
FIG. 1A
illustrates a one-ordered SDM with an integrator Z
−1
10
;
FIG. 1B
illustrates a two-ordered SDM with two integrators
11
and
12
connected in serial; and
FIG. 1C
illustrates a multi-ordered (at least three orders) SDM with plural integrators
13
,
14
, and
15
.
Though the integrator with high-order noise shaping function can provide a higher resolution, the SDM becomes unstable when the number of integrators (orders) exceeds two. This is due to signal overload accumulated in the integrator in the later stage.
The architecture of the cascaded SDM realizes high-ordered noise shaping with multiple low-ordered SDMs. Multi-stage noise shaping (MASH) architecture of this type is shown in
FIGS. 2A-2B
. In
FIG. 2A
, high-ordered noise shaping is realized with two cascaded low-ordered SDMs
20
and
21
; whereas in
FIG. 2B
, high-ordered noise shaping is realized with three cascaded low-ordered SDMs
22
,
23
, and
24
. However, cascaded SDMs are still troubled with overloads.
The output SNR will degrade due to restraints imposed by non-ideal conditions (values) of the analog components. This is due to the gain mismatch effect of the cascaded SDM. An alternative solution is to provide an improved cascaded SDM, that is, the second-ordered SDM cascaded by a first-ordered SDM (Second-Ordered First-Ordered Cascaded architecture; SOFOC), as shown in FIG.
3
.
The architecture shown in
FIG. 3
basically converts a MASH architecture cascaded with three-stage first ordered SDMs
22
,
23
, and
24
as shown in
FIG. 2B
, into a MASH architecture having second-ordered SDM
30
in the preceding stage and a first-ordered SDM
32
in the succeeding stage to realize a cascaded SDM. The input of the SDM of the stage
32
receives a quantization noise −Q
1
of the SDM of the preceding stage
30
. The conversion function is as follows:
Y
1
=X+(1−Z
−1
)
2
Q
1
Y
2
=−Q
1
+(1−Z
−1
) Q
2
Y=Y
1
+(1−Z
−1
)
2
Y
2
=X+(1−Z
−1
)
3
Q
2
where Y
1
is a first-stage digital output, and Y
2
is a second-stage digital output; −Q
1
is a first-stage quantization noise, −Q
2
(not shown in
FIG. 3
) is a second-stage quantization noise, Y is an overall digital output signal, and X is an analog input signal.
Refer to
FIG. 2B
for a comparison with the MASH architecture. When the quantization noise of the preceding stage cannot be fully eliminated due to a gain mismatch effect, the overall digital output signal of the MASH architecture is as follows:
Y
(
MASH
)
=
α
Y
1
+
β
(
1
-
Z
-
1
)
Y
2
+
γ
(
1
-
Z
-
1
)
2
Y
3
=
α
X
+
(
α
-
β
)
(
1
-
Z
-
1
)
Q
1
+
(
β
-
γ
)
(
1
-
Z
-
1
)
2
Q
2
+
_
γ
(
1
-
Z
-
1
)
3
Q
3
_
where Y
3
is a third-stage digital output, and −Q
3
is a third-stage quantization noise; and &agr;≠&bgr;≠&ggr; due to gain mismatch, whereas &agr;=&bgr;=&ggr; when the gains of the preceding and succeeding stages match.
In the SOFOC architecture, when the quantization noise of the preceding stage cannot be fully eliminated due to gain mismatch effect, the overall digital output signal of the SOFOC architecture is as follows:
Y
(
SOFOC
)
=
α
Y
1
+
β
(
1
-
Z
-
1
)
2
Y
2
=
α
X
+
(
α
-
β
)
(
1
-
Z
-
1
)
2
Q
1
+
β
(
1
-
Z
-
1
)
3
Q
2
_
If in gain match, then &agr;=&agr;=&ggr;; and assume &agr;=1, then Y(SOFOC)=Y, being the optimal status for analog components. Under the gain mismatch effect, after the processing of the second-order noise shaping factor, that is, (1−Z
−1
)
2
, the leaking noise generated in an SOFOC architecture becomes smaller than the first-order leaking noise generated in a MASH architecture. Therefore, the SDM in the SOFOC architecture demonstrates better resistance to the sensitivity (gain mismatch) of analog components. That is to say, the performance of the SDM in the SOFOC has lower dependency upon the idealization of analog components.
However, since the preceding stage of an SOFOC SDM is a second-ordered SDM rather than a highly stable first-ordered SDM, and the input of the succeeding stage of the SDM is the quantized noise of the preceding stage of the SDM, the cascaded second stage integrator still suffer from overload due to significant input signals.
It is known from the above that an oversampled SDM, both of a classical and cascaded architecture, is subject to instability. Therefore, it becomes essential to enhance the stabilization of the oversampled SDM.
The following three techniques have been proposed to resolve overload problems: (1) limiting an input dynamic range; (2) inserting a gain scaling means into an SDM, for reducing linear-proportionally of the dynamic range of the system signal as shown in
FIG. 4
; and (3) using automatic gain control (AGC), for linear-proportionally adjusting of the dynamic range of the system signal with the input signal magnitude.
The aforementioned three conventional techniques all linearly reduce the operating signal swing range of the modulators to protect the integrator from instability due to significant signal accumulation. But a limiting input dynamic range technique will limit the applicable range of the modulator; whereas the AGC technique or gain scaling insertion technique will reduce the overall system SNR, because the output end of the system has to compensate the previous gain scaling (or signal reduction).
In the SOFOC architecture of
FIG. 4
, a signal gain scaling apparatus
40
is further arranged between a second-ordered SDM
30
and a first-order SDM
32
for linearly reducing the amplitude of the error quantization signal −Q
1
; and a linear gain recovering device
42
is arranged at the output of the first-order SDM
32
. The conversion function is represented as:
Y
1
=X+(1−Z
−1
)
2
Q
1
Y
2
=−jQ
1
+(1−Z
−1
) Q
2
Y=Y
1
+1/j (1−Z
−1
)
2
Y
2
=X+1/j (1−Z
−1
)
3
Q
2
where j<1. It is known from the architecture of
FIG. 4
that the input signal −jQ
1
of the second-stage modulation unit becomes smaller, because of the linear signal scaling apparatus
40
, to prevent the second-stage modulation unit from integrator overload. Thus, the quantized noise of the overall output function is compensated by the gain recovering device
42
, and is amplified, thus becoming the greater quantized noise 1/j (1−Z
−1
)
3
Q
2
). Therefore, the overall SNR is red
Ho Chian C.
Hsieh Hsun-Chang
Kuo Chung J.
Birch & Stewart Kolasch & Birch, LLP
Industrial Technology Research Institute
Young Brian
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