Sigma-delta modulator capable of compensating a time delay

Details Sigma-delta modulator capable of compensating a time delay Sigma-delta modulator capable of compensating a time delay

2007-03-09

2009-02-24

Mai, Lam T (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S155000

Reexamination Certificate

active

07495593

ABSTRACT:
A sigma-delta modulator is disclosed. The sigma-delta modulator includes a first integrator, a second integrator, an analog-to-digital converter, a digital-to-analog converter (DAC), and a compensating device. The first integrator receives an input signal for generating a first output signal. The second integrator receives the first output signal for generating a second output signal. The ADC converts the second output signal into a digital modulation signal. The DAC converts the digital modulation signal into an analog feedback signal. The analog feedback signal is transmitted to the first integrator and the second integrator. The compensating device is for compensating the analog feedback signal for a time delay caused by a feedback loop from the ADC through the DAC to the first integrator.

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IEEE ISSCC, Session 9, Switched-Capacitor ΔΣ Modulators, (2005), Paper 9.6 pp. 176-177, 591, 132-133, 567-568, Paper 9.7 pp. 178-179, 592, 134-135, 569, Paper 10.1 pp. 570.
Cherry et al., “Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion: Theory, Practice and Fundamental Performance Limits,” Kluwer Academic Publishers, pp. 74-103.

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