Sigma-delta modulator

Details Sigma-delta modulator Sigma-delta modulator

2002-04-08

2003-06-10

Young, Brian (Department: 2817)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S144000, C341S159000

Reexamination Certificate

active

06577259

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application is based on and hereby claims priority to PCT Application No. PCT/DE00/03535 filed on Oct. 6, 2000 and German Application No. 199 48 374.4 filed on Oct. 7, 1999, the contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
The invention relates to a sigma-delta modulator for converting time-discrete samples into corresponding analog signals.
In digital/analog converters such as are used, for example, in digital radio communication devices, a digital input signal with 2
n
signal states and a fixed sampling frequency f
a
is usually changed into an analog signal which should correspond as well as possible to the digital signal in the frequency range from −f
a
/2 to +f
a
/2.
It is particularly at high bit widths n that the number of signal states to be achieved by analog circuit technology represents a significant problem. For this reason, a digital signal is interpolated by digital filters and so-called sigma-delta modulators are used which distinctly reduce the bit width n of a digital signal at increased sampling frequency and transform the quantization noise generated by this into previously unused frequency ranges. In this arrangement, structures which achieve noise shaping, which are comparable to a shaping which can be achieved by higher-order IIR (Infinite Impulse Response) filters, are particularly efficient.
In the case of the sigma-delta modulators, there are two approaches for achieving noise shaping. According to a first approach, higher-order feedback loops are used, which allows a reduction to up to two signal states (1-bit signal technique), but leads to possible instabilities at high input signals above third-order noise shaping. Excesses very easily occur in the range of values. To counteract this, an amplitude-reduced input signal and state memories with clipping characteristics are used in practice, which allows an empirically determined stability of the circuit to be achieved.
According to another approach, first- and/or second-order structures are cascaded which are multi-stage structures and, as a result, exhibit a stable operating characteristic.
Known structures of sigma-delta modulators operate serially and at a high clock rate, since the sigma-delta modulators are feedback structures with non-linear elements. A detailed representation of the theory and the structure of sigma-delta modulators are provided in S. R. Norswothy, R. Schreier, G. Temes: “Delta-Sigma Data Converters, Theory, Design and Simulation”, IEEE Press 1997, ISBN 0-7803-1045-4.
Due to the noise shaping aimed for, the sigma-delta modulator of a typical digital/analog converter operates in a time- and value-discrete manner at a clock frequency which is much higher than the maximum signal frequency used. It has feedback filters and nonlinear substructures which prevent these structures from being implemented at a lower clock rate.
One aspect of the invention is based on the object of developing a structure for a sigma-delta modulator which operates at a lower clock rate and thus more inexpensively and with power-saving technology.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the object is achieved by a first-order sigma-delta modulator being parallelized and a higher-order cascaded sigma-delta modulator being created out of a number of parallelized first-order structures.
One aspect of the invention achieves the result that sigma-delta modulators can be achieved which have a lower sampling clock rate and thus less circuit expenditure and are more inexpensive.


REFERENCES:
patent: 5225835 (1993-07-01), Majima et al.
patent: 5369403 (1994-11-01), Temes et al.
patent: 5416483 (1995-05-01), Matsuya
patent: 5870048 (1999-02-01), Kuo et al.
patent: 6255977 (2001-07-01), Jelonnek et al.
patent: 6323794 (2001-11-01), Okuda et al.
patent: 0506079 (1992-09-01), None
patent: 0551690 (1993-07-01), None
Norsworthy et al., “Delta-Sigma Data Converters-Theory, Design, and Simulation,” IEEE Circuits & Systems Society, The institute of Electrical and Electronics Engineers, Inc., New York, IEEE Press, 1997.

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