Sigma-delta data conversion employing quantization error...

Details Sigma-delta data conversion employing quantization error... Sigma-delta data conversion employing quantization error...

2002-10-11

2003-11-04

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

Reexamination Certificate

active

06642874

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to sigma-delta data converters, and in particular to a sigma-delta data converter providing improved quantization noise shaping through error feedback.
2. Description of Related Art
Sigma-Delta ADC Architecture
FIG. 1
depicts a prior art sigma-delta analog-to-digital converter (ADC)
10
including a sample and hold (S/H) circuit
12
, a sigma-delta modulator
14
, and a digital decimator
16
, for digitizing an analog input signal A
IN
to produce an output data sequence D representing the analog input signal. S/H circuit
12
samples the A
IN
signal on each pulse of a clock signal (CLOCK) at a rate much higher than the A
IN
signal bandwidth to produce a sequence of discrete analog samples x
n
supplied as input to sigma-delta modulator
14
. Sigma-delta modulator
14
responds to each pulse of the CLOCK signal by generating an element of an output sequence y
n
. When each element of the y
n
sequence is, for example, a single bit wide, sigma-delta modulator
14
sets the y
n
bit to a logical 1 increasingly more frequently than to a logical 0 as A
IN
increases in magnitude so that the density of 1's in the y
n
sequence is proportional to the magnitude of A
IN
. When the y
n
sequence is more than one bit, sigma-delta modulator
14
generates higher values of y
n
with increasing frequency as A
IN
increases. Decimator
16
carries out the function of a finite impulse response (FIR) filter, filtering the y
n
sequence to produce a sequence of elements
D
n
=
∑
i
=
-
N1
N2
⁢
 
⁢
f
i
⁢
 
⁢
y
n
-
i
Sigma-delta modulator
14
includes an analog summing circuit
18
, an analog filter
20
having a discrete transfer function H(z
−1
), an m-bit ADC converter
22
, and an m-bit digital-to-analog converter
24
. Filter
20
filters the output sequence an of summer
18
to produce an analog sequence b
n
. ADC
22
digitizes b
n
to produce y
n
. For example when m=1, and b
n
is above a threshold level, ADC
22
sets y
n
to a 1 and otherwise sets y
n
to a 0 when b
n
is below the threshold level. DAC
24
therefore drives its analog output signal c
n
to the maximum expected level of x
n
when y
n
is a 1 and drives c
n
to the minimum expected level of x
n
when y
n
is a 0. The feedback loop formed by devices
18
-
24
tries to keep b
n
at the ADC's threshold level and to do that, it has to drive y
n
to a 1 with a frequency that increases with the amplitude of A
IN
. Modulator
14
operates in a generally similar manner when m>1 except that ADC
22
and DAC
24
adjust y
n
and c
n
with m-bit resolution.
Sigma-Delta DAC
FIG. 3
illustrates a conventional sigma-delta DAC
30
for converting a sequence of p-bit data words x
n
into an analog output signal A. DAC
30
includes a sigma-delta demodulator
32
for converting x
n
into an m-bit wide output sequence y
n
. An m-bit DAC
34
drives its output A′ high or low depending on the state of y
n
, and an analog filter
36
removes out-of-band quantization noise from the A′ signal to produce the A signal. Sigma-delta demodulator
32
includes a summer
38
for generating a data value a
n
=x
n
−c
n
, a digital filter
40
for filtering the a
n
data sequence with a transfer function H(z
−1
) to produce a data sequence b
n
, and a digital quantizer
42
for generating an element of the y
n
sequence in response to each corresponding element of the b
n
sequence. Each element of the y
n
sequence has m bits, where m is more than zero and less than the number of bits of elements of the b
n
sequence, and each element of the y
n
sequence represents the same quantity as a corresponding element of the b
n
sequence, but with lower resolution. The y
n
sequence is provided as the c
n
sequence input to summer
38
which
where N
1
and N
2
are integers and FIR filter coefficients f
−N1
−f
N2
are numbers selected to give decimator
16
selected low pass or band pass characteristics to eliminate aliasing and out-of-band quantization noise. Decimator
16
reduces the number of elements of the D
n
sequence by a factor of k to produce output sequence D. That is, only every kth element of the D
n
sequence becomes an element of the D sequence.
FIG. 2
is a timing diagram illustrating a simple example wherein k=3, i has values of the set {−1, 0, 1}, and all filter coefficients f
−1
=f
0
=f
1
=1. Thus in this example each element of the D sequence is equal to a sum of a separate set of k=three elements of the y
n
sequence, although in practice filter coefficients f will often have values other than 1 to provide desired low pass or band pass filter characteristics.
ADC
10
has an input range of 0-3 volts, and the A
IN
signal ramps linearly from 0 to 3 volts during 36 CLOCK cycles, and the x
n
signal is a step-wise approximation of the A
IN
signal. Note that the density of 1's in the y
n
sequence increases with the magnitude of x
n
. In this simple example, decimator
16
sums the preceding three y
n
sequence bits to produce each element of the D sequence. A digital data word having n bits represents a magnitude with “n-bit resolution” since the word can have any of 2
n
different combinations of bit states, each of which represents a different magnitude. In the example of
FIG. 2
, the output sequence D of ADC
10
represents input signal magnitude A
IN
with 2-bit resolution because the 2-bit wide elements of the D sequence can be any of 2
2
values of the set {0, 1, 2, 3}. We can increase the resolution of ADC
10
by increasing k. For example, if decimator
16
sums y
n
sequence elements during k=255 clock cycles, then elements of the D sequence would be 8-bits wide and could represent 2
8
different signal magnitudes. However to avoid aliasing, the clock signal frequency should be at least k times the Nyquist frequency of the A
IN
signal. subtracts the c
n
sequence from the most significant bits of the x
n
sequence. Sigma-delta DAC
30
can control the magnitude of output analog signal A with substantially higher resolution than DAC
34
, provided that the frequency at which x
n
sequence are provided is substantially higher than the highest frequency component of output signal A.
Quantization Noise
The ADC
22
of FIG.
1
and digital quantizer
42
essentially “round off” the value represented by their input b
n
sequences to produce their output sequences y
n
. For example when b
n
can represent any integer value between 0 and 7, and y
n
is only one bit wide, a y
n
value of 0 is equivalent to a b
n
value of 0 and y
n
value of 1 is equivalent to a b
n
value of 7. When b
n
has some value between 0 and 7, ADC
22
or digital quantizer
42
essentially rounds b
n
down to 0 or up to 7 when determining whether to set y
n
to a 0 or a 1. Thus, for example, when b
n
has value 2, y
n
will be set to 0 and the difference between the values represented by corresponding b
n
and y
n
sequence element (called the “quantization error” of the sigma-delta modulator or demodulator) will be b
n
−y
n
=2−0=2. When b
n
has value 6, y
n
will be set to a 1 (representing 7) and the quantization error will be 6−7=−1. The quantization error can be reduced by increasing the width m of y
n
but cannot be eliminated since in a sigma-delta modulator or demodulator because y
n
always has fewer bits than b
n
.
To improve the accuracy of ADC
10
or DAC
30
, it is beneficial to reduce the effects of quantization error on DUT. The quantization error introduced by ADC
22
or digital quantizer
32
can be modeled as additive noise sequence e
n
as illustrated in FIG.
4
. The z-transform Y(z
−1
) of sequence y(n) can be expressed as a linear function of the z-transforms X(z
−1
) and E(z
−1
) of analog or digital input sequence x(n) and error sequence e
n
.
Y
⁢
 
⁢
(
z
-
1
)
=
H
⁢
 
⁢
(
z
-
1
)
&i

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