Sigma-delta-d/a-converter

Details Sigma-delta-d/a-converter Sigma-delta-d/a-converter

2000-09-05

2001-07-03

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S144000

Reexamination Certificate

active

06255977

ABSTRACT:

TECHNICAL FIELD
The invention is directed to a sigma-delta D-A converter with N stages, in which the nth stage, where n=1, 2, 3 . . . N, comprises a first adder which adds a use signal or use signals x(k) with an error signal err
n
(k- 1) to an input signal e
n
(k), a quantizer which quantizes the input signal e
n
(k) to an output signal y
n
(k) according to a predetermined quantization function, and a second adder which adds the input signal e
n
(k) with the inverted output signal y
n
(k) to x
n
(k), and supplies it to a delay device which sends the signal xn(k) to the first adder as an error signal err
n
(k−1) with a delay by a clock period according to the preamble of claim
1
.
PRIOR ART
A sigma-delta D-A converter of the generic type is known from the book “Delta Sigma Data Converter, Theory, Design and Simulation”, by Steven R. Norsworthy, Richard Schreiner and Gabor C. Temes, IEEE Press 1997, ISBN 0-7803-1045-4. Known sigma-delta D-A converters of this type have the disadvantage that they are not asympotically stable and, in short, are astable. In this respect, unwanted limit cycles may be generated by the sigma-delta D-A converter when the input signal of the converter is zero, i.e., when the converter is not excited. These limit cycles may possibly assume high amplitudes which are audible as NF amplitude, for example, in modulation pauses of a wanted broadcast signal, or which degrade the signal-to-noise ratio. Further, without an input signal, sigma delta D-A converters generate a “digital noise”, as it is called, i.e., a zero input signal (x(k)=0 for all k>=k
0
) is not uniquely imaged on a zero output signal, but on a sequence of output values which waver around the zero position and accordingly generate noise. The reason for this resides in ideal discrete integrators and in the utilized quantizers. The effects mentioned above impair the functionality and usefulness of such D-A converters.
DESCRIPTION OF THE INVENTION, OBJECT, SOLUTION, ADVANTAGES
It is the object of the present invention to provide an improved sigma-delta D-A converter of the type mentioned above which eliminates the above-mentioned disadvantages.
This object is met by a sigma-delta D-A converter of the type mentioned above having the characterizing features of claim
1
.
For this purpose, it is provided, according to the invention, that an amount reducer is provided between the second adder and the delay device, which amount reducer leaves the signal x
n
(k) unchanged when x
n
(k)=0 and otherwise lowers the amount |x
n
(k)| of the signal x
n
(k) by at least the smallest representable numerical unit, wherein the quantization function of the quantizer of the nth stage of the sigma-delta D-A converter is expressed as follows:
y
n
⁡
(
k
)
=
{
2
(
1
-
n
)
,
if
⁢
 
⁢
e
n
⁡
(
k
)
>
2
-
n
0
,
if
⁢
 
⁢
abs
⁢
 
⁢
(
e
n
⁡
(
k
)
)
≤
2
-
n
-
2
(
1
-
n
)
,
if
⁢
 
⁢
e
n
⁡
(
k
)
<
-
2
-
n
where abs( ) is the absolute value function. This has the advantage that the sigma-delta D-A converter according to the invention has an asymptotically stable behavior, i.e., all optional starting values of the integrators of the sigma-delta D-A converter reach the zero state in infinity. Further, the necessary quantity of output stages of the D-A converter is minimized, which reduces expenditure on subsequent circuits.
Preferred further developments of the device are described in claims
2
to
4
.
A use signal of the nth stage, where n>1, is advisably the output signal x
n-1
(k) of the second adder of the (n−1)th stage, wherein the nth stage (n−1) has differentiators following the quantizer when there are two or more stages.
A conclusive combination of the output signals of all stages is achieved in that the first (N−1) stages, where N>1, each have a third adder which follows the quantizer in the case of the first stage and which follows the differentiators in the case of the second to (N−1)th stage, wherein every third adder of the first to (N−2)th stages is connected with the respective third adder of the next highest stage and the third adder of the (N−1)th stage is connected with the last differentiator of the Nth stage.


REFERENCES:
patent: 5084702 (1992-01-01), Ribner
patent: 5181032 (1993-01-01), Ribner
patent: 5982317 (1999-11-01), Steensgaard-Madsen
“Delta Sigma Data Converter, Theory, Design and Simulation”, Von Stev R. Norsworthy, et al IEEE Press 1997, ISBN 0-7803-1045-4.

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