Sigma delta class D architecture which corrects for power...

Details Sigma delta class D architecture which corrects for power... Sigma delta class D architecture which corrects for power...

2005-09-13

2005-09-13

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

Reexamination Certificate

active

06943717

ABSTRACT:
A sigma delta class D device that uses a low pass filter to smooth the output waveform and eliminate high frequency switching noise from the feedback value includes: a first summing node having a positive input coupled to a signal input node; a second summing node having a first positive input coupled to an output of the first summing node and having an output coupled to a signal output node; a low pass filter having an input coupled to the output of the second summing node; an analog to digital converter having an input coupled to an output of the low pass filter; a third summing node having a positive input node coupled to an output of the analog to digital converter and a negative input node coupled to the output of the first summing node; and a feedback device coupled between an output of the third summing node and a negative input of the first summing node.

REFERENCES:
patent: 5030952 (1991-07-01), Ledzius et al.
patent: 5392040 (1995-02-01), Hayashi
patent: 5392282 (1995-02-01), Kiema
patent: 6271781 (2001-08-01), Pellon

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