Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2002-08-08
2003-09-02
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
Reexamination Certificate
active
06614375
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to sigma-delta analog-to-digital converters, and, more particularly, to a sigma-delta analog-to-digital converter having an improved low power multiplexer.
BACKGROUND OF THE INVENTION
High resolution sigma-delta analog-to-digital converter (ADC) technology has become a key analog circuit technology for digital audio and telecommunications applications. Sigma-delta ADC's are capable of providing precision greatly in excess of sixteen bits. For low power applications, however, it is desirable to decrease the power consumption for the overall circuit.
Many conventional sigma-delta ADCs include one or more sigma-delta integrators, a comparator and a differential reference multiplexer. As is known, the sigma-delta integrators couple to receive inputs from any analog external source needing a conversion from analog to digital. The comparator couples to receive the output of sigma-delta integrator for implementation of the quantization step to generate a differential pair of decision signals.
As in most designs, these sigma-delta integrators require a reference voltage to operate. Thus, a reference voltage is generated using an active circuit such as an amplifier. To reduce power consumption, however, it is desirable to eliminate the active circuit. Most known designs replace the active circuit with reference voltage applied across passive filter circuit including a filter capacitor to generate reference multiplexer inputs. The reference multiplexer receives these reference multiplexer inputs along with the decision signals from the comparator. A first set of output signals from the reference multiplexer provide a shadow bit scheme and a second set of reference output signals provide either an inverted or non-inverted differential reference feedback to the sigma-delta integrator depending upon the comparator decision signals. These reference output signals represent the quantized decision of the sigma-delta integrator multiplied by the reference voltage; whereby, the sigma-delta integrator maintains the average value of the feedback to be equal to the reference voltage input.
The leads corresponding to the second set of reference output signals, however, each have a parasitic capacitance associated with it that generates noise in the sigma-delta ADC as a result of the reference multiplexer's dual modes of operation. In particular, in a first mode, the reference inputs directly feed into the reference outputs and, as a result, the reference voltage signal is not inverted, such that the reference voltage outputs remain the same. When the reference multiplexer switches from the first mode to the second mode, however, a first parasitic capacitor charges from the negative reference input to the positive reference input and a second parasitic capacitor discharges from the positive reference input to the negative reference input.
The second mode of operation cross couples the reference inputs to be fed into differing reference outputs such that the reference voltage is effectively inverted. As a result, when the reference multiplexer switches from the second mode to the first mode, the first parasitic capacitor discharges from the positive reference input to the negative reference input and the second parasitic capacitor charges from the negative reference input to the positive reference input.
Charging either the first or the second parasitic capacitor draws charge off the filter capacitor which reduces the reference input voltage slightly. Due to the random nature of charging and discharging the filter capacitor, low frequency noise results in the reference input voltage signal. This low frequency noise on the filtered reference degrades the SNR performance of the ADC.
Due to this degradation in performance, there is a need to decrease, if not eliminate, the noise in the reference voltage input signals in a sigma-delta ADC given the design constraints of low power consumption.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of sigma-delta analog-to-digital converters (ADC), the present invention teaches a low power, sigma-delta ADC having an improved reference multiplexer that eliminates noise in the reference signal. The sigma-delta ADC includes a passive filter circuit connected to receive a differential reference voltage input. The improved differential multiplexer couples to the passive filter circuit to receive the reference voltage signal. This differential multiplexer includes three modes of operation: (1) direct coupling of the differential input to the differential output, (2) cross-coupling of the differential input to the differential output, and (3) setting the differential output to a fixed voltage to discharge the parasitic capacitance in the differential output every clock cycle. This last mode eliminates the noise of the reference voltage signal and ultimately the sigma-delta ADC. A sigma-delta integrator receives the differential output from the differential multiplexer. A comparator couples to the output of the sigma-delta integrator to provide a decision signal to the differential multiplexer for enabling and disabling the first and second modes of operation. A clocking signal fed to the differential multiplexer is responsible for enabling and disabling the third mode of operation that discharges the parasitic capacitance in the differential outputs of the differential multiplexer.
Advantages of this design include but are not limited to a low noise, low power sigma-delta ADC.
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Brady III Wade James
Mosby April M.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Young Brian
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