Sigma-delta analog-to-digital converter array

Details Sigma-delta analog-to-digital converter array Sigma-delta analog-to-digital converter array

2001-11-02

2002-12-17

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S155000

Reexamination Certificate

active

06496128

ABSTRACT:

FIELD OF INVENTION
The present disclosure relates to a sigma-delta analog-to-digital converter array and, in particular, a cascaded two-stage sigma-delta analog-to-digital converter.
BACKGROUND OF INVENTION
Many xDSL applications require analog-to-digital converters (abbreviated as AD converters hereafter) with a high resolution and good bandwidth. In this connection, what are known as pipeline architectures are used with several flash AD converters. Pipeline architectures of this type permit very high bandwidths and correspondingly high sampling rates with good signal resolution. As a rule, however, pipeline architectures need automatic calibrating mechanisms which have to be provided on the same chip as the AD converter array and therefore increase the complexity of the circuit and the size of silicon junction needed.
Consequently, it is an advantage to use sigma-delta converters, which are capable of achieving a higher dynamic range by oversampling, although this usually results in a reduced signal bandwidth. In order to increase the available signal bandwidth without increasing the sampling rate, it is therefore necessary to reduce the oversampling rate (OSR). Satisfactory operation at low oversampling rates is only possible if the quantization noise induced by the quantizers used in sigma-delta converters is a sufficiently low.
However, the one-bit quantizers used in one-bit sigma-delta converters generate relatively high quantization errors and it is only with great difficulty that a good signal-to-noise ratio can be achieved with a one-bit sigma-delta converter at a low oversampling rate. Furthermore, although they require only a small silicon junction, one-bit sigma-delta converter architectures need powerful supply currents because of the relatively high sampling rates.
On the other hand, multi-bit sigma-delta converter architectures, which are basically slightly larger than one-bit sigma-delta architectures, consume significantly less current, since they enable lower sampling frequencies. By using a multi-bit feedback, a high signal-to-noise ratio can be achieved at only low oversampling rates. Multi-bit sigma-delta converters can therefore be used in all applications that require both high resolution and a high converter speed. Hence, multi-bit sigma-delta converters bridge the gap between the flash converters mentioned above, which enable high speeds with limited resolution, and one-bit sigma-delta converters, which permit high resolution at average speeds.
Various aspects of operating a high-performance multi-bit sigma-delta converter pose a challenge. One of these aspects is the problem of developing an architecture that will enable efficient operation of the internal AD and digital-to-analog or digital/analog (DA) converters of the sigma-delta converter in terms of junction surface area. Since the DA and AD converters are usually connected in series within the feedback loop of the corresponding sigma-delta converter architecture, the maximum permissible conversion time for each converter corresponds to only half the clock time. Consequently, applications that are efficient in terms of surface area (e.g., pipeline structures) cannot be used for internal AD converters because of their natural latency or natural reaction time.
Conventional single-stage, multi-bit sigma-delta converters with internal quantization higher than 5 bit, for example, also present a disadvantage in terms of the silicon junction required although they offer considerable advantages in terms-of power consumption.
Another problem inherent in multi-bit sigma-delta converter architectures is the fact that these architectures must necessarily have one or more multi-bit DA converters in the feedback loop but a multi-bit feedback of this type gives rise to problems of linearity.
In order to solve this problem, it was proposed in “An Improved Sigma-Delta Modulator Architecture”, T. C. Leslie and B. Singh, IEEE Proceedings ISCAS '90, pages 372-375, May 1990, that the lower-value bits be clipped from the multi-bit output signal of the AD converter and only the highest value bit be applied to the feedback loop, which means only having to use a one-bit DA converter in the feedback branch. The lower-value bits are digitally processed and combined with the output signal of the sigma-delta converter in order to minimise any errors in the feedback signal which might be incurred as a result of clipping the lower-value bits.
Another way of reducing quantization noise when using multi-bit sigma-delta converter architectures is to use several sigma-delta converter stages connected in a cascaded array. With cascaded sigma-delta converter architectures of this type, the quantization errors of one stage are processed in the subsequent stage and the digital output signals of the individual stages are digitally processed in order to suppress noise. Cascaded sigma-delta converters are also known as MASH sigma-delta converters.
FIG. 5
shows a simplified block diagram of a cascaded, two-stage sigma-delta converter architecture of this type, specifically of the type described in “A 50 MHz Multibit Sigma-Delta Modulator for 12b 2 MHZ A/D Conversion”, B. P. Brandt, B. A. Wolley, IEEE Journal of Solid-State Circuits, vol. 26, December 1991. This architecture comprises two sigma-delta converter stages or sigma-delta modulators
1
and
2
connected in a cascaded array, the first converter stage
1
corresponding to a second-order one-bit sigma-delta converter and the second converter stage
2
to a first-order multi-bit sigma-delta converter. Accordingly, as illustrated in
FIG. 5
, the first converter stage
1
comprises two integrators
6
,
9
in the form of SC-Filters (switched capacitor), which are disposed together with a 1-bit AD converter
10
in the forward path of the first converter stage
1
. As is usually the case with sigma-delta converters, the digital output signal of the 1-bit AD converter
10
is applied to adders
4
and
7
via a 1-bit DA converter
11
in the feedback branch in such a way that the respective difference between the output signal of the 1-bit AD converter
10
and the corresponding signal in the forward path is applied to the integrators
6
and
9
. Via an adder
16
, the second converter stage
2
receives as an input signal the differential signal between the analog output signal of the 1-bit DA converter
11
and the input signal of the 1-bit AD converter
10
(i.e., the quantization error induced by 1-bit quantization is applied to the second converter stage
2
). The structure of the second converter stage
2
corresponds to a single-stage 3-bit sigma-delta converter and accordingly comprises an adder
18
, an integrator
20
, a 3-bit AD converter
21
. and a 3-bit DA converter
22
, connected as illustrated in FIG.
5
. The output signals supplied by the two converter stages
1
and
2
are digitally processed by a noise suppression logic
3
so that a digital output signal Y(z) corresponding to the analog input signal X(z) is emitted. Each of the integrators
6
,
9
and
20
may be provided in the form of SC filters and are represented by the transfer function 1/(1−z
−1
) or z
−1
/(1−z
−1
), for example.
In the circuit illustrated in
FIG. 5
, the high sensitivity in terms of the accuracy of the DA converters in the feedback branch, which limits the linearity and resolution of the sigma-delta converter architecture, is reduced only by dint of the fact that a multi-bit quantizer is used in the second converter stage
2
while the more critical quantizer of the first converter stage
1
is a one-bit quantizer.
In the publication “A Cascaded Sigma-Delta Pipeline A/D Converter with 1.25 MHz Signal Bandwidth and 89 dB SNR”, T. L. Brooks, D. H. Robertson, D. F. Kelly, A. Del Muro, S. W. Harston, IEEE Journal of Solid-State Circuits, vol. 32, pages 1896-1906, December 1997, a variant of this cascaded sigma-delta converter architecture is proposed, whereby a sigma-delta converter stage is connected in a cascaded array with a pipeline AD converter. The

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