Sigma-delta analog to digital converter architecture based...

Details Sigma-delta analog to digital converter architecture based... Sigma-delta analog to digital converter architecture based...

2002-09-11

2004-03-16

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S155000

Reexamination Certificate

active

06707409

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to analog to digital converters, and more specifically, to a delta-sigma modulation analog to digital converter with increased resolution and stability.
DESCRIPTION OF RELATED ART
Two basic techniques for implementing an analog-to-digital converter (ADC) are the open-loop technique and the feedback technique. An open-loop converter generates a digital code directly upon application of an input voltage and is generally asynchronous in operation. A feedback converter generates a sequence of digital codes from an input signal, reconverts the digital codes to an analog signal and feeds back the analog signal.
A typical first-order sigma-delta ADC is shown in
FIG. 1
as
100
. An analog signal received at an input
102
is applied to a subtracting circuit
104
, where a feedback signal (to be described later) is subtracted from the analog signal received at the input. The resulting signal is integrated in an integrator, and the resulting integrated output is applied to a quantizer
108
to produce a digital number representing a level of the integrated output. The digital number output by the quantizer
108
is applied to a digital-to-analog converter (DAC)
110
to provide the feedback signal noted above. The digital number output by the quantizer
108
is also applied to a digital FIR filter
112
, where it is low-pass-filtered, and to a downsampler
114
, where it is downsampled. The resulting digital signal is output at an output
116
.
Within the context of ADC's based on the sigma-delta architecture there are three basic approaches to increase the resolution: 1) Increase the oversampling ratio, 2) Increase the order of the modulator, 3) Increase the quantizer resolution. Those approaches have led to improvements of ADC resolution throughout the last decade; however, designs based upon those principles have been optimized, and further improvements will likely be modest. The prior art has concentrated mostly on employing band-pass filters in the modulator. However, a band-pass approach reduces the slope of the SNR increase versus modulator order by a factor of two. Therefore, such designs incur additional complication and concomitant performance penalties.
The following three U.S. patents are believed to be the most relevant to the subject matter of the present application.
U.S. Pat. No. 5,027,120, “Delta-sigma converter with bandpass filter for noise reduction ”
Analogue signals are converted to digital data by use of a Sigma-Delta modulator including a pair of bandpass filters and a feedback loop including a digital to analogue converter. The tendency of such a circuit to instability is reduced or eliminated by making small variations in the phase of a clock controlling feedback pulses relative to a clock controlling data output pulses. As an alternative, corrections may be made to the feedback pulses by an additional feedback loop providing pulses for correcting the feedback pulses. That patent covers the idea of bandpass signal conversion technique and its instability reduction.
U.S. Pat. No. 5,179,380, “One-bit sigma-delta modulator with improved signal stability”
The one-bit sigma-delta modulator with improved signal stability disclosed includes, in order, a first anti-aliasing filter, a chopper, a second anti-aliasing filter, and a one-bit modulator. The chopper and one-bit modulator are driven by a clock generator. The chopper is introduced to provide a carrier upon which the signal may ride, thereby eliminating dc stability problems. The first anti-aliasing filter eliminates aliasing from the chopper, and the second anti-aliasing filter eliminates aliasing from the one-bit modulator. The second anti-aliasing filter may be eliminated if the frequency of the chopper is an exact integer submultiple of the sampling frequency of the one-bit modulator. This invention may drive a decimation filter, to provide a low cost analog-to-digital converter.
That patent covers the general idea of an input signal modulation in order to decrease instability problems caused by a DC offset. It specifically limits itself to a one-bit modulator and does not cover multi-bit sigma-delta modulators and their stability issues.
U.S. Pat. No. 5,442,353, “Bandpass sigma-delta analog-to-digital converter (ADC), method therefor, and receiver using same”
A bandpass sigma-delta analog-to-digital converter (ADC) (
10
) includes first (
11
) and second (
12
) band pass sigma-delta modulators, and a digital filter (
13
) connected to digital outputs thereof. In the illustrated embodiment, the first band pass sigma-delta modulator (
11
) is a second-order, single bit bandpass modulator, and the second bandpass sigma-delta modulator (
12
) is a first-order, multiple-bit modulator. Coefficients in feedback paths of the first (
1
) and second (
12
) modulators are derived from a transfer function of the digital filter. In one embodiment, a receiver (
50
) for a system such as frequency modulation (FM) radio converts an intermediate frequency (IF) analog signal to digital in-phase (I) and quaternary (Q) signals using the bandpass sigma-delta ADC (
10
). That patent covers only the idea of bandpass signal conversion technique, and its instability reduction.
U.S. Pat. No. 4,994,804 “Double integration delta-sigma modulation analog to digital converter”
The abstarct of that patent states “A delta-sigma modulation analog to digital converter for converting an analog input signal to a digital output signal. The converter includes an input circuit for receiving the analog input signal, a clock generator for generating a very high frequency clock signal with first and second phases, a first switching circuit coupled to the input circuit for modulating the analog input signal with the very high frequency clock signal, an integration circuit coupled to the first switching circuit for integrating the modulated input signal and generating a noise signal, a second switching circuit coupled to the integration circuit both for demodulating the integrated modulated input signal and modulating the noise signal with the very high frequency clock signal, a quantizing circuit coupled to the second switching circuit for responsive to the demodulated input signal and the modulated noise signal for generating the digital output signal including a separable portion corresponding to the modulated noise signal and a feedback circuit coupled between the quantizing circuit and the integration circuit both for generating a feedback signal corresponding to the digital output signal and feeding the feedback signal to the integration circuit.”
That patent covers the idea of modulating an input signal with a very high frequency clock signal similar to the method of the present invention. However, the referenced patent employs a conventional integrator as the modulator filter which, by consequence, fails to achieve the favorable noise shaping properties of the present invention.
SUMMARY OF INVENTION
It will be apparent from the above that a need exists in the art to improve the resolution of the sigma-delta ADC without reducing performance or increasing complexity to the degree experienced in the prior art. It is therefore an object of the present invention to provide an architecture to do so.
To achieve the above and other objects, the present invention uses a “Mirrored Integrator” (MI) in the modulator. The modulator itself could be of the N-th order and it could employ an M-bit quantizer and M-bit Digital-to-analog converter (DAC). The new approach retains the low-pass sigma-delta slope of the SNR. In addition, the noise-shaping property of the sigma-delta converter employing a MI is that the quantization noise is shaped toward the low-frequency portion of the spectrum (in opposition to conventional Sigma-delta converters where the quantization noise is shaped toward the high-frequency portion of the spectrum). In the new approach, the output signal may be passed through a high-pass filter (in opposition to a conventional sigma-delta converter in which the signal is pass

Affiliated with

Also associated with

Rating

Sigma-delta analog to digital converter architecture based... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Sigma-delta analog to digital converter architecture based..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sigma-delta analog to digital converter architecture based... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3223624