Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2002-02-04
2002-12-24
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
Reexamination Certificate
active
06498573
ABSTRACT:
The invention relates to a sigma-delta A/D converter with minimal current load of the reference voltage sources.
FIG. 1
shows a block circuit diagram of a sigma-delta A/D converter according to the prior art. The sigma-delta A/D converter receives an analog input signal at the input E, which is fed to a subtraction element S. In the subtraction element S the output signal of a multi-bit D/A converter is subtracted from the analog input signal and is fed to an integrator. The integrator integrates the input signal and outputs the integrated signal to a quantizer. The quantizer is an analog-to-digital converter with a low resolution which outputs the digitized output signal to an output A of the sigma-delta A/D converter. The digitized output signal is connected via a feedback line to the input of the multi-bit D/A converter. The digitized output signal of the quantizer is converted by the multi-bit D/A converter into an analog signal and is subtracted in the subtraction element S from the input signal at the input E.
FIG. 2
shows an embodiment of a sigma-delta A/D converter employing SC circuitry (SC switched capacities: switchable capacitors). The prior art sigma-delta A/D converter shown in
FIG. 2
is a fully differential sigma-delta A/D converter having two signal inputs V
INA
and V
INB
. Also provided are reference voltage sources V
REFP
and V
REFN
which can be connected by controllable switching devices to capacitors C
1A
, C
2A
, . . . C
LA
as well as capacitors C
1B
, C
2B
, . . . C
LB
. The capacitors may furthermore be connected by switching devices to the analog signal inputs V
INA
, V
INB
.
On the output side, the capacitors C
1A
, C
2A
, . . . C
LA
as well as C
1B
, C
2B
, . . . C
LB
can be connected by switching devices n and a common ground line to ground V
GND
or to an integrator.
In the sigma-delta A/D converter shown in
FIG. 2
, the integrator contains an operational amplifier with one inverting and one non-inverting input as well as two output lines, with integration capacitors CINT being connected between the signal inputs and signal outputs of the operational amplifier in each case. Connected downstream of the integrator is a quantizer for analog-to-digital conversion of the voltage between the two output lines of the operational amplifier. The digitized signal present at the output of the quantizer is fed via a feedback line to a control logic element which supplies control signals for controlling the switching devices.
During a sampling phase PHl
1
, the capacitors C
1A
, C
2A
, C
LA
are connected by switches on the one hand to the first analog input line V
INA
and on the other hand to ground V
GND
. During the sampling phase PHL
1
, the capacitors C
1B
, C
2B
, . . . C
LB
are connected by switching devices on the one hand to the second analog input signal V
INB
and on the other hand to ground V
GND
. During the sampling phase, all switches indicated by “PHL
1
” in
FIG. 2
are closed.
Upon completion of the sampling phase PHL
1
, the switches indicated by PHl
1
in
FIG. 2
are opened and the capacitors C
1A
, C
2A
, . . . C
LA
are connected by the switches indicated by PHL
2
to the non-inverting input (+) of the operational amplifier and to the first integration capacitor CintA for charge transfer. At the same time, the capacitors C
1B
, C
2B
, . . . C
LB
are switched by the switches indicated by PHL
2
to the inverting input (−) of the operational amplifier and to the second integration capacitor C
intB
for charge transfer. At the same time, in each case the left capacitor plates of the capacitors C
1A
, C
2A
, . . . C
LA
and C
1B
, C
2B
, . . . C
LB
are connected to the reference voltage source V
REFP
or to the reference voltage source V
REFN
respectively in accordance with the control instructions generated by the control logic element.
Upon completion of the integration phase PHL
2
, an output voltage V
OUTP
(i) is present at the output of the integrator, i.e. between the two output lines of the operational amplifier, which output voltage depends on the preceding value V
OUTP
(i−1), the analog input voltage V
INA
(i−½), the number of capacitors C
jA
whose left capacitor plate is connected to the positive reference voltage source V
REFP
during the integration phase, and the number n (i) of capacitors C
jA
whose left capacitor plate is connected to the negative reference voltage source V
REFN
during the integration phase.
The output voltage V
OUTP
(i) is obtained here using the following equation:
V
OUTP
(
i
)
=
V
OUTP
(
i
-
1
)
+
V
INA
(
i
-
1
/
2
)
·
L
·
C
jA
C
int
-
p
(
i
)
·
&LeftBracketingBar;
V
REFP
&RightBracketingBar;
·
C
jA
C
int
+
n
(
i
)
·
&LeftBracketingBar;
V
REFN
&RightBracketingBar;
·
C
jA
C
int
⩵
=
V
OUTP
(
i
-
1
)
+
V
INA
(
i
-
1
/
2
)
·
L
·
C
jA
C
int
-
(
p
(
i
)
-
n
(
i
)
)
·
V
REF
·
C
jA
C
int
with
V
REF
=
&LeftBracketingBar;
V
REFP
&RightBracketingBar;
=
&LeftBracketingBar;
V
REFN
&RightBracketingBar;
;
(
1
)
The number of capacitors C
jA
whose left capacitor plate is connected to the positive reference voltage source V
REFP
during the integration phase is obtained here using the following equation:
p
(
i
)
=
round
[
L
/
2
·
(
1
+
V
DIG
(
i
)
V
REF
)
]
<=
L
for
V
DIG
(
i
)
>=
0
;
(
2
)
where V
DIG
is the output signal of the quantizer.
The number of capacitances C
jA
whose capacitor plate is connected to the negative reference voltage source V
REFN
during the integration phase is obtained using the following equation:
n
(
i
)
=
round
[
L
/
2
·
(
1
-
V
DIG
(
i
)
V
REF
)
]
<=
L
for
V
DIG
(
i
)
<=
0
;
(
3
)
where V
DIG
is the output signal of the quantizer. The total number of capacitances whose left capacitor plate in each case is connected to the positive reference voltage source during the integration phase and of capacitances whose left capacitor plate is connected to the negative reference voltage source V
REFN
during the integration phase is constant here.
p
(
i
)+
n
(
i
)=
L
=const., (4)
where L is the total number of capacitors.
So that the total charge is fully integrated, all capacitors are connected to the input of the operational amplifier during the integration phase.
The load of the reference voltage sources V
REFP
, V
REFN
with the prior art sigma-delta A/D converter shown in
FIG. 2
is greatly signal-dependent.
For V
DIG
(i)~V
INA
(i) and V
INA
(i)>0, the charge transfer at the positive reference voltage source caused by the analog input signal V
INA
(i) is calculated using the following equation:
&AutoLeftMatch;
&LeftBracketingBar;
dq_V
REFP
(
i
)
&RightBracketingBar;
=
p
(
i
)
·
(
V
REFP
-
V
INA
(
i
)
)
·
C
jA
=
round
[
L
/
2
+
L
/
2
·
V
DIG
(
i
)
V
REF
]
·
(
V
REFP
-
V
INA
(
i
)
)
·
C
jA
~
(
L
/
2
·
V
REF
-
L
/
2
·
V
INA
(
i
)
+
L
/
2
·
V
DIG
(
i
)
-
L
/
2
·
V
INA
(
i
)
·
V
DIG
(
i
)
V
REF
)
·
C
jA
~
L
/
2
·
C
jA
·
V
REF
·
(
1
-
V
INA
(
i
)
2
V
REF
)
;
(
5
)
The charge transfer at the negative reference voltage source is obtained using the following equation:
&AutoLeftMatch;
&LeftBracketingBar;
dq_V
REFN
(
i
)
&RightBracketingBar;
=
n
(
i
)
·
(
&LeftBracketingBar;
V
REFP
&RightBracketingBar;
+
V
INA
(
i
)
)
·
C
jA
=
(
L
-
round
[
L
/
2
+
L
/
2
·
V
DIG
(
i
)
V
REF
]
)
·
(
&LeftBracketingBar;
V
REFN
&RightBracketingBar;
+
V
INA
(
i
)
)
·
(
~
(
L
/
2
·
V
REF
+
L
/
2
·
V
INA
(
i
)
-
L
/
2
·
V
DIG
(
i
)
~
L
/
2
·
V
INA
(
i
)
·
V
DIG
(
i
)
V
REF
)
·
Infineon - Technologies AG
Withrow & Terranova, P.L.L.C.
Young Brian
LandOfFree
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