Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2001-08-13
2002-09-24
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S019000, C257S189000, C257S190000
Reexamination Certificate
active
06455871
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to a SiGe MODFET with a metal-oxide gate and method fabricating the same. More particularly, the present invention relates to a technology for improving the operation speed of a SiGe MODFET and reducing its non-linear operation characteristic caused by single channel, by increasing the mobility of carriers in the SiGe MODEFT with a metal-oxide film.
BACKGROUND OF THE INVENTION
In recent CMOS technology, the line width is reduced to 130 nm and the storage capacity of 1 G-byte has been achieved. With continued development efforts, around the year of 2012, the minimum line width will be reduced to 35 nm and the integration level will reach at 10
10
cm
−2
. At the same time, there have been a lot of efforts to implement system-on-chip by improving the function of CMOS in various ways in order to commercialize BiCMOS including a SiGe HBT (Hetero-structure bipolar transistor). Meanwhile, efforts have been actively made to accomplish intra-chip and inter-chip communication through implementation of photoelectric integration circuits incorporating photoelectric devices to silicon integration circuits. As the chip scale has reach a degree in which control using classical physics and statistics becomes very difficult, it has been found that the conventional technology could not control the repeatability and uniformity. Under these circumstances, next-generation semiconductor technology for overcoming the problems has been in need.
FIG. 1
is a cross-sectional view illustrating the device structure of a conventional SiGe MODFET.
Referring now to
FIG. 1
, a thin silicon buffer film
120
is grown on a silicon substrate
110
. Then, a SiGe channel layer
130
and a silicon cap layer
140
are grown on the thin silicon buffer film
120
. Next, after a silicon insulating (or oxide) film
150
is deposited, gate
160
and source-drain
171
and
172
are sequentially formed. Although this type of MODFET can be easily manufactured, there is a problem that a channel is also formed in the silicon cap layer
140
due to an inversion phenomenon when a high gate-drain voltage is applied. In addition, as it is difficult to adjust the thickness of the silicon cap layer
140
remaining after the oxide film
150
is formed and to control diffusion of impurity through the oxide film
150
, there are problems that the operational characteristic of the gate is not uniform and impurity or Ge is concentrated with high concentration at the interface between the oxide film
150
and the SiGe channel layer
130
, which causes a leakage current and lowers reliability. Further, as a hetero-junction is disturbed by high-temperature process, defects tend to generat at the interface between the SiGe channel layer
130
and the silicon cap layer
140
. These problems pose a process constraint that the gate oxide film
150
must be formed at a low temperature.
As another example, there is a conventional method in which a base and a collector are self-aligned on the single-crystalline silicon substrate by means of SEG (selective epitaxial growth) and SOI (silicon-on-insulator) technology, and a hetero-junction structure of SiGe/Si/SiO
2
is formed by implanting Ge and then oxidizing the silicon. Although there is an advantage that the MODFET having a high concentration carrier can be easily manufactured by simple method, the method have the problem that defects tend to generate between the SOI and the epitaxial layer, and the problem caused by the high concentration ion implantation should be solved. Also, this method has limitations in fabricating devices because of the high-temperature annealing process used in the formation of SiGe and an oxide film.
SUMMARY OF THE INVENTION
The present invention is contrived to solve the above problems and an object of the present invention is therefore to provide a method of fabricating a SiGe MODFET with a metal oxide film gate which is capable of significantly improving the operation characteristics of device by preventing the leakage current caused by the mismatch of the lattice constant and by the precipitation of Ge during the formation of the oxide film. Another object of the invention is to eliminate the impurity diffusion problem of a high-temperature process by adopting a low-temperature process, especially for the eptaxial growth process. A semiconductor device according to the present invention has a structure fabricated by utilizing an epitaxial growth technology of atomic layers and by forming a gate oxide film having high-speed characteristic and excellent electrical characteristics. As the device is fabricated by the process compatible with conventional CMOS fabrication technology, it has a high reliability.
According to one aspect of the present invention, a SiGe MODEFT device including a silicon buffer layer, a SiGe channel layer and a silicon cap layer sequentially formed on a silicon substrate, being characterized by further comprising a second silicon buffer layer and a SiGe buffer layer sequentially formed between said silicon buffer layer and said SiGe channel layer a temperature lower than that is used to form said silicon buffer layer is provided.
According to another aspect of the invention, a method for fabricating a SiGe MODEFT device comprising a silicon buffer layer, a SiGe channel layer and a silicon cap layer sequentially formed on a silicon substrate, being characterized by comprising the steps of sequentially growing a second silicon buffer layer and a SiGe buffer layer between said silicon buffer layer and said SiGe channel layer, wherein said second buffer layer and said SiGe buffer layer are formed at a temperature lower than that is used to form said silicon buffer layer so that the defects caused by the mismatch of the lattice constants of each of said layers are constrained within said second buffer layer and said SiGe buffer layer is provided.
When a stress due to the difference of lattice constant is absent, the energy gaps of Si, Ge or SiC are 1.12 eV, 0.7 eV, and 2.3 eV, respectively, and their lattice constants are 5.43 Å, 5.64 Å, and 4.37 Å, respectively. When the impurity concentration below 10
16
cm
−3
, the mobility of electrons in silicon semiconductor is about 1500 cm
2
/Vs. If the doping concentration is increased by 10~100 times, however, the mobility of electrons is reduced to about one over several hundredth of the above mobility. SiGe, however, has advantages that the electron mobility is high as ~2000 cm
2
/Vs when the impurity concentration is 10
18
cm
−3
. In case of pseudo-morphic, as the collision area of carriers is reduced by transformation of band-gap, the mobility is increased to about 3000~4000 cm
2
/Vs. Meanwhile, though the mobility of 3C-SiC is high as 4000 cm
2
/Vs and stable, it should have a thickness smaller than the threshold thickness so that defects are not generated due to the difference of the lattice constant from silicon.
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patent: 5534713 (1996-07-01), Ismail et al.
patent: 5698869 (1997-12-01), Yoshimi et al.
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patent: 5891769 (1999-04-01), Liaw et al.
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Sadek, et al.;Design of Si/SiGe Heterojunction Complementary Metal-Oxide-Semiconductor Transistors;IEEE Transactions on Electron Devices, vol. 43, No. 8, Aug. 1996, pp. 1224-1232.
Kang Jin Yeoung
Kim Hong Seung
Lee Seung Yun
Shim Kyu Hwan
Chaudhuri Olik
Electronics and Telecommunications Research Institute
Jacobson & Holman PLLC
Pham Hoai
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