SiGe layer having small poly grains

Details SiGe layer having small poly grains SiGe layer having small poly grains

2006-11-07

2006-11-07

Wilczewski, Mary (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

C257S197000, C257S213000, C257S565000, C438S235000

Reexamination Certificate

active

07132700

ABSTRACT:
A disclosed embodiment is a method for fabricating a structure in a semiconductor die, the method comprising depositing a silicon buffer layer over a single crystalline region and at least one isolation region at a first pressure, where the silicon buffer layer is continuous, i.e. comprises small poly grains, over the at least one isolation region. The method further includes forming a silicon germanium layer over the silicon buffer layer at a second pressure, where the silicon germanium layer is also continuous, i.e. comprises small poly grains, over the at least one isolation region. In one embodiment, the first pressure is less than the second pressure. In other embodiments, a structure is fabricated according to the above method.

REFERENCES:
patent: 5731241 (1998-03-01), Jang et al.
patent: 6534802 (2003-03-01), Schuegraf
patent: 6861308 (2005-03-01), U'Ren et al.

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