Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2001-08-31
2004-08-03
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S357000, C257S344000
Reexamination Certificate
active
06770921
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to semiconductor devices. More particularly, it pertains to enhancing devices that are made from diverse polycrystalline substances so as to inhibit undesired cross diffusion and provide a gate electrode connection.
BACKGROUND OF THE INVENTION
A semiconductor has a conductivity that can be increased by introducing impurities into the semiconductor. Impurities that add more holes to a semiconductor are called acceptors. A semiconductor with an abundance of holes is called a p-type semiconductor. Impurities that add more electrons are called donors. A semiconductor with an abundance of electrons is called an n-type semiconductor.
One useful electronic device is the diode. The diode is made by forming a p-type semiconductor material adjacent to an n-type semiconductor material. Holes reside in abundance in the p-type semiconductor material but not in the n-type semiconductor material. Electrons reside in abundance in the n-type material but not in the p-type material. This situation creates a discontinuity in the concentration of holes and electrons and allows holes and electrons to diffuse. A metallurgical bond between the p-type and n-type regions forms a depletion region with an electromagnetic field of a magnitude that inhibits the further diffusion of electrons and holes. This effect can be overcome when desired to allow the diode to act as an electronic switch from which other electronic devices can be built.
Modern semiconductor processes may require a p-type semiconductor material to be adjoined to an n-type semiconductor material, but not for the purpose of forming a diode. Such a situation occurs in CMOS inverters where a n-type polycrystalline silicon must connect with a p-type polycrystalline silicon in a diode-free fashion (i.e., short to one another). This is typically done with a metal deposited on both n/p-type of polycrystalline silicon connection said materials. Unfortunately, this connection allows holes and/or electrons to move from their respective starting points through the metal into the oppositely doped material; this cross diffusion is undesirable.
FIG. 1A
is a cross-sectional view taken from the front of a semiconductor structure
100
and
FIG. 1B
is a cross-sectional view taken from the top of the semiconductor structure
100
according to the prior art. The semiconductor structure
100
includes a gate oxide layer
108
that overlies an n-channel active area
102
, a field region
118
, and a p-channel active area
120
. The n-channel active area
102
includes a p-type well
122
containing highly doped n-type areas
104
, as shown in FIG.
1
B. These highly doped areas
104
form a drain region and a source region of an n-channel transistor. The highly doped n-type areas
104
are doped with donor impurities. The p-channel active area
120
includes an n-type well
124
containing highly doped p-type areas
104
, as shown in FIG.
1
B. The highly doped p-type areas
104
are doped with acceptor impurities, and these highly doped p-type areas
104
form a drain region and a source region of a p-channel transistor.
The n-channel active area
102
also includes an n-type polycrystalline silicon strip
110
A forming a transistor gate for the n-channel transistor, and the p-channel active area
120
includes a p-type polycrystalline silicon strip
110
B forming a transistor gate for the p-channel transistor. A gate cap
112
, which is formed from a nonconductive material, overlies both the n-type polycrystalline silicon strip
110
A and the p-type polycrystalline silicon strip
110
B. A spacer
114
surrounds a portion of the semiconductor structure
100
as shown in FIG.
1
B. Both the spacer
114
and the gate cap
112
electrically isolate and structurally support the transistor gates from other conductive layers (not shown) in the semiconductor structure
100
In complementary semiconductor structures, such as CMOS, dual-doped polycrystalline silicon is used to simultaneously form p-channel and n-channel devices. Particularly, an SRAM cell uses a single polycrystalline line to form a gate electrode for both the pull-up device and the pull-down device. This single polycrystalline line is dual-doped with both acceptor impurities and donor impurities shown as portions
110
A, B in FIG.
1
A.
The n-type polycrystalline silicon strip
110
A abuts against the p-type polycrystalline silicon strip
110
B. As explained hereinbefore, a diode may undesirably form from the contact of the n-type polycrystalline silicon strip
110
A and the p-type polycrystalline silicon strip
110
B.
To prevent diode formation, a conductive material
113
is deposited on top of the n-type polycrystalline silicon strip
110
A and the p-type polycrystalline silicon strip
110
B. This conductive material
113
shorts the two types of polycrystalline silicon strips
110
A, B so they are at the same potential.
The problem with this approach is that placing the conductive material
113
on top increases the height of the semiconductor device. Another problem is that the conductive material
113
can create undesired cross-diffusion. Cross-diffusion occurs when impurities from one type of polycrystalline silicon diffuse up through the conductive material
113
and diffuse down to the other type of polycrystalline silicon. This movement of impurities undesirably transforms the designed semiconductor characteristic of the polycrystalline silicon. A further problem is that certain conductive materials may decompose during processing, which forms an undesired dielectric layer that may create parasitic effects.
Typical structures of conduction material
113
result in cross diffusion. This cross diffusion is proportional to the amount of surface area between the doped polycrystalline silicon and conductive material. Therefore, the less contact area between doped polycrystalline silicon and conductive layers the lower the cross diffusion.
Thus, what is needed are structures, devices, and methods for enhancing semiconductor devices to inhibit cross diffusion and enable solutions for gate electrode connections.
SUMMARY OF THE INVENTION
An illustrative aspect of the present invention includes a semiconductor structure. The semiconductor structure includes a dual-doped polycrystalline silicon layer, which comprises a p-type strip and an n-type strip. The p-type strip has a top, a bottom, two sides, and two ends. The n-type strip also has a top, a bottom, two sides, and two ends. One of the ends of the p-type strip abuts against one of the ends of the n-type strip. The semiconductor structure also includes an inhibitor strip that adjoins a portion of one of sides of the p-type strip and a portion of one of the sides of the n-type strip.
REFERENCES:
patent: 4716131 (1987-12-01), Okazawa et al.
patent: 5087582 (1992-02-01), Campbell et al.
patent: 5217913 (1993-06-01), Watabe et al.
patent: 5382532 (1995-01-01), Kobayashi et al.
patent: 5464789 (1995-11-01), Saito
patent: 5956617 (1999-09-01), Kimura et al.
patent: 6133082 (2000-10-01), Masuoka
patent: 6583518 (2003-06-01), Trivedi et al.
patent: 2002/0188631 (2002-12-01), Tiemann et al.
Abbott Todd R.
Trivedi Jigish D.
Wang Zhongze
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Rose Kiesha
Zarabian Amir
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