Sidewall spacers for CMOS circuit stress relief/isolation and me

Details Sidewall spacers for CMOS circuit stress relief/isolation and me Sidewall spacers for CMOS circuit stress relief/isolation and me

1986-03-17

1988-03-01

Carroll, James

357 231, 357 239, 357 2311, 357 41, 357 52, 357 54, 357 55, 357 56, 357 73, H01L 2702, H01L 2978, H01L 2906, H01L 2934

Patent

active

047290064

ABSTRACT:
A method for forming fully recessed (planar) isolation regions on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate with mesas formed therein, forming low viscosity sidewall spacers of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches in the substrate adjacent to the mesas with TEOS; and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops. These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

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