Sidewall-sealed poly-buffered LOCOS isolation

Details Sidewall-sealed poly-buffered LOCOS isolation Sidewall-sealed poly-buffered LOCOS isolation

1992-08-05

1994-11-29

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 70, 437 72, H01L 2176, H01L 2131

Patent

active

053690516

ABSTRACT:
A method for forming LOCOS isolation regions which includes the steps of forming a polysilicon buffer layer between the pad oxide layer and the nitride layer and forming a sidewall seal around the perimeter of the active moat regions prior to the field oxidation step. The resulting field oxide isolation region has reduced oxide encroachment into the active moat region.

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Clarence W. Teng, et al., "Optimization of Sidewall Masked Isolation Process", IEEE Jour. of Sol. State Circuits, vol. SC-20, No. 1, Feb. 85 P44-51.

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