Sidewall-sealed and sandwiched poly-buffered locos isolation met

Details Sidewall-sealed and sandwiched poly-buffered locos isolation met Sidewall-sealed and sandwiched poly-buffered locos isolation met

1992-09-29

1994-03-15

Fourson, George

Fishing, trapping, and vermin destroying

437 70, H01C 2176

Patent

active

052945634

ABSTRACT:
This is a method for forming LOCOS isolation regions which includes the steps of forming a first silicon nitride layer between the pad oxide layer and a polysilicon buffer layer and a second nitride layer over the polysilicon buffer layer. In addition, the method for forming LOCOS isolation regions can include the additional steps of forming a sidewall seal around the perimeter of the active moat regions prior to the field oxidation step. The resulting field oxide isolation regions have reduced oxide encroachment into the active moat region.

REFERENCES:
patent: 4923563 (1990-05-01), Lee
Martin, R. "Spacer for Improved Local Oxidation Profile", Xerox Disclosure Journal vol. 12, No. 5 Oct. 9, 1987, pp. 251-3.
Tzu-Yin, C., et al, Non Overlapping Super Self Aligned BiCMOS with 87 ps Low Power ECL AT&T Bell Labs.
Wolf S., Silicon Processing for the VLSI Era, vol. 2, #1990 pp. 35-41.

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