Semiconductor device manufacturing: process – Chemical etching – Having liquid and vapor etching steps
Reexamination Certificate
1999-08-26
2002-03-05
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Having liquid and vapor etching steps
C438S710000, C438S712000, C438S723000, C438S745000
Reexamination Certificate
active
06352934
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to a method for forming dual sidewall oxides for shallow junction formation.
2. Description of the Related Art
Semiconductor memories typically include an array region and a support region. The array region includes a memory array comprising a plurality of memory cells. Each memory cell includes a capacitor for storing a digital bit. The capacitor of the memory cell is typically written to or read from by switching on an access transistor which connects the capacitor to a bitline. The access transistor is often enabled by activating a wordline which functions as the transistor gate. The transistor gates (or wordlines) are formed in both the array region and the support region.
The support region includes “support” components and circuitry needed for the operation of the memory chip. The support region includes transistor devices which also include gates. Gate structures for both the array region and the support region are fabricated simultaneously. However, there are differences between the requirements of the gates in the array region and the gates of the support region. For example, an oxide layer may be formed on lateral surfaces of the gate structures for curing etch damage and forming bird beak structures (i.e., rounding sharp corners). A thinner oxide layer is needed in the support region for shallow junction formation and a thicker oxide is needed in the array region. The thicker oxide in the array region expends some amount of thermal budget. Typically, the thick oxide layer on surfaces of the gate structures in the array region and the thin oxide layer on surfaces of the gate structures in the support region are formed in separate steps.
Therefore, a need exists for a method for providing a single oxidation process for both an array region and a support region for a semiconductor device.
SUMMARY OF THE INVENTION
A method for forming dielectric protection in different regions of a semiconductor device, in accordance with the present invention, includes forming structures in a first region and a second region. A dielectric layer is grown on surfaces of the structures and in between the structures in the first region and the second region. The dielectric layer is damaged in the second region to provide an altered layer which is etchable at a faster rate than the dielectric layer in the first region. The dielectric layer in the first region and the altered layer in the second region are etched to provide a dielectric protection layer having a first thickness in the first region and a second thickness in the second region.
In other methods, the first region may be an array region and the second region may be a support region, and the first thickness may be greater than the second thickness. The step of growing a dielectric layer on surfaces may include the step of growing an oxide layer on sidewalls of the structures and in between the structures. The step of damaging the dielectric layer in the second region to provide an altered layer may include the step of exposing the dielectric layer in the second region to a plasma condition. The plasma condition may include a HBr/O
2
reactive ion etch. The plasma condition preferably smooths a surface of the dielectric layer in the second region. The step of damaging the dielectric layer in the second region to provide an altered layer may include the step of illuminating the dielectric layer in the second region with radiation. The radiation may include ultraviolet radiation. The step of etching the dielectric layer may include the step of etching with hydrofluoric acid.
In accordance with the invention, a method for forming dielectric protection in different regions of a semiconductor device includes forming structures in a first region and a second region, growing a first dielectric layer on surfaces of the structures and in between the structures in the first region and the second region, and damaging the first dielectric layer in the second region to provide an altered layer which is etchable at a faster rate than the first dielectric layer in the first region. The first dielectric layer is etched in the first region to provide a first thickness in the first region. The altered layer is etched to remove the altered layer from the second region. A second dielectric layer is grown having a second thickness in the second region such that the first region includes the first thickness of the first dielectric layer and the second thickness of the second dielectric layer.
In other methods, the first region may be an array region and the second region may be a support region. The first dielectric layer and the second dielectric layer may include an oxide layer. The step of damaging the first dielectric layer in the second region to provide an altered layer may include the step of exposing the first dielectric layer in the second region to a plasma condition. The plasma condition may includes a HBr/O
2
reactive ion etch. The plasma condition preferably smooths a surface of the first dielectric layer in the second region. The step of damaging the first dielectric layer in the second region to provide an altered layer may include the step of illuminating the first dielectric layer in the second region with radiation. The radiation may include ultraviolet radiation. The step of etching may include the step of etching with hydrofluoric acid.
In accordance with the invention, a method for forming protective oxides in an array region and a support region of a semiconductor memory includes providing a semiconductor substrate having a gate oxide layer formed thereon, patterning gate stacks in the support region and in the array region and oxidizing the gate stacks and the gate oxide layer to form a sidewall oxide on lateral surfaces of the gate stacks and increase a thickness of the gate oxide layer between the gate stacks. A resist is formed over the array region, and the sidewall oxide and the gate oxide layer are damaged in the support region to provide an altered layer which is etchable at a faster rate than the sidewall oxide and the gate oxide layer in the array region. The resist is removed, and the sidewall oxide and the gate oxide layer are etched in the array region and the altered layer in the support region to provide a dielectric protection layer having a first thickness in the array region and a second thickness in the support region.
The first thickness is preferably greater than the second thickness. The step of damaging the sidewall oxide and the gate oxide layer in the support region to provide an altered layer may include the step of exposing the sidewall oxide and the gate oxide layer in the support region to a plasma condition. The plasma condition may include a HBr/O
2
reactive ion etch. The plasma condition preferably smooths a surface of the sidewall oxide and the gate oxide layer in the support region. The step of damaging the sidewall oxide and the gate oxide layer in the support region to provide an altered layer may include the step of illuminating the sidewall oxide and the gate oxide layer in the support region with radiation. The radiation may include ultraviolet radiation. The step of etching may include the step of etching with hydrofluoric acid.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
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Infineon - Technologies AG
Perez-Ramos Vanessa
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