Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
2000-09-29
2003-02-04
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S214000, C257S220000, C257S267000, C257S274000, C257S243000, C257S244000
Reexamination Certificate
active
06515317
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method for significantly increasing the pixel density and blue light sensitivity in a charge couple device (CCD). More particularly, the present invention involves the use of sidewall as well as surface gates to increase pixel density without decreasing total gate area. Portions of the gates occupy vertical sidewalls, thus a relatively larger portion of the horizontal area is available for openings in the polysilicon gates to admit more light into the channel region. This arrangement permits the density of the pixel array to increase without any loss of sensitivity. The process of the present invention makes it possible to achieve active storage area, progressive scan CCD image sensors incorporating vertical anti-blooming device structures.
BACKGROUND OF INVENTION
A charge couple device (CCD) functions as an active matrix to absorb light and convert it to electrons. Such are used for example as the electronic film in digital still cameras (DSC).
Charge-coupled devices are solid-state devices that, when formed in arrays and used with suitable imaging hardware, can be used to capture video images.
FIGS. 1
,
2
A and
2
B illustrate prior art 4-phase charge-coupled device structure.
FIG. 1
is a top view showing horizontal signal lines running over the channel stop regions and making connections to every fourth gate. Four gates over a channel region comprise a pixel, so the drawing shows three complete pixels. The gates are comprised of overlapping but electrically isolated polysilicon lines running vertically. Holes in the polysilicon lines allow light energy to enter and induce an electron—hole pair when the photon energy exceeds the Si bandgap. Electrical fields cause the electrons to be swept into the channel regions under the gates. Once the image is stored, it is read out much like a shift register would read out. Signals
1
through
4
force the stored charge to move to the right as two adjacent gates are always turned on together. Holding the voltage high on gates
1
and
2
while keeping the voltage low on gates
3
and
4
creates a potential well under gates
1
and that collects photo-induced charge for the pixel. Changing the voltage on
1
to low and on
3
to high forces the charge to move from under the
1
and
2
gates to under the
2
and
3
gates. Reversing polarity on the
2
and
4
gates moves the charge under the
3
and
4
gates. The process is repeated until all the original charge in the pixel is now in the new pixel. Of course, any charge in the previous pixel is now in this pixel. This comprises one transfer cycle. The transfer cycles are repeated until all pixels have been read out, each being moved across the array. Extremely high transfer efficiency is desired because several thousand transfers may be required for the charge to reach the edge of the array.
FIG. 2A
is a cross-sectional view through line A—A of
FIG. 1
showing the overlap of the polysilicon gates along the channel.
FIG. 2B
is a cross-sectional view through line B of
FIG. 1
across several channel regions. A peaked P well is present as a vertical antiblooming device. Recess oxidation (ROX) with P-type channel stops acts as isolation between adjacent channel regions. If CCD's are overexposed (the potential wells under the gates can not hold all the charge), the extra charge will spill over into adjacent pixels. The antiblooming device shown is of the vertical antiblooming type. When collected charge in the channel reaches the well, the excess charge is collected in the substrate.
Dark current is another problem associated with CCD's. Dark current is noise resulting from electrons generated by thermal vibration, by surface states, or in bulk defects. These electrons may collect under the gates, causing white spots and columns in the resulting readout. Dark current is minimized by elimination of all mechanisms, other than light absorption, that are capable of generating electron-hole pairs. Therefore silicon defects, metallic impurities, and surface states must be controlled.
SUMMARY OF INVENTION
The invention provides a method for increasing the pixel density in a charge coupled device, with no diminution of sensitivity, by providing a semiconductor substrate having antiblooming profile formed therein, etching trenches in the silicon, forming N-channels along sidewalls of the trenches, forming a P+ region, a region of silicon doped to about 10
17
atoms/cm
3
with an impurity such as B, Al, Ga, or In, to act as channel stop at the bottom of the trenches; successively forming P
1
and P
3
gates, the polysilicon transfer gates of the charge coupled device structure, and finally finishing by providing conventional contact, wiring, and passivation.
Where configured in a photosensitive manner, the invention provides for increased pixel density without loss of light sensitivity or resolution. In such configurations, the invention also obtains enhanced sensitivity to blue light. The increased sensitivity to blue light is achieved by maximizing the ratio of detection area to non-detection area and by reducing the thickness of the polysilicon gates. A further aspect of the invention is that the polysilicon line extends down along a first sidewall of a trench formed in the substrate, along the bottom of the trench, and up along the second sidewall as well as running along the top surface of the substrate. The P
1
and P
3
gates overlap predominantly on the sidewalls and bottom of the trench and to a lesser extent on the top surface of the substrate, so charge transfer occurs mainly along the sidewall gate. Utilization of the sidewall as gates allows for an increase in pixel area without a decrease in total gate area. This aspect of the invention allows more horizontal area to be available for openings in the polysilicon gates, thus admitting more light into the array.
The invention realizes a charge couple device characterized by having a series of vertical FETs creating a CCD scan chain in the sidewalls of trenches formed in a silicon substrate, CCD clock gates perpendicular to and filling the trenches and having narrow bands running across the plateau regions between trenches, charge generation regions on the tops of the plateaus; and charge transport regions along the trench side walls, wherein the sides of the trenches and the region over the plateau form a common charge collection well.
Another unique feature of the invention is the elimination of recess oxidation (ROX) isolation. Only the channel stop diffusion, and to a lesser extent the gate oxide, is used for channel isolation.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 5086010 (1992-02-01), Kimura
patent: 5159419 (1992-10-01), Hosack
patent: 5173756 (1992-12-01), Wong et al.
patent: 5223726 (1993-06-01), Yamada et al.
Bazan Gregory
Klaasen William A.
Mann Randy W.
Abate Esq. Joseph P.
Abraham Fetsum
Connolly Bove & Lodge & Hutz LLP
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